Glossary

140 of 140 · showing Novice definitions

AEC-Q100

The Automotive Electronics Council’s failure-mechanism-based stress test qualification for ICs, with temperature grades 0 to 3.

All three levels

Beginner. The standard stress tests a chip must pass before carmakers will use it.

Novice. The Automotive Electronics Council’s failure-mechanism-based stress test qualification for ICs, with temperature grades 0 to 3.

Expert. Defines test groups and sample sizes (for example HTOL on 77 parts from each of 3 lots, zero fails). It qualifies reliability; functional safety is covered separately by ISO 26262.

always-on domain

A power domain that stays powered in every mode. It holds wake-up logic, timers, and the power controller.

All three levels

Beginner. The small part of the chip that never sleeps, so it can notice a button press or a message and wake everything else.

Novice. A power domain that stays powered in every mode. It holds wake-up logic, timers, and the power controller.

Expert. Kept small and built from low-leakage cells. Its signals must cross switched domains through always-on buffers, and its leakage sets the device’s floor current in deep sleep.

analog front end (AFE)

Amplifiers, filters, and an ADC that condition biosignals such as ECG or neural activity, which range from tens of microvolts to millivolts.

All three levels

Beginner. The circuit that picks up the body’s tiny electrical signals and makes them large and clean enough to measure.

Novice. Amplifiers, filters, and an ADC that condition biosignals such as ECG or neural activity, which range from tens of microvolts to millivolts.

Expert. Designed for input-referred noise in µVrms at µA currents, rejection of large electrode offsets via AC coupling, and low 1/f noise through large input devices or chopping. Noise efficiency factor is the usual figure of merit.

And-Inverter Graph (AIG)

A directed acyclic graph of two-input AND nodes whose edges may be inverted. Any combinational logic can be expressed this way.

All three levels

Beginner. A way of drawing any logic using only one kind of gate (AND) plus ‘not’ markers.

Novice. A directed acyclic graph of two-input AND nodes whose edges may be inverted. Any combinational logic can be expressed this way.

Expert. The core data structure in ABC and many modern tools. Structural hashing keeps it free of duplicate nodes; node count and depth correlate with mapped area and delay. Rewriting, balancing, mapping and SAT-based equivalence checking all operate on it.

ASIC

Application-specific integrated circuit: a custom chip fabricated from your own design, with high up-front cost and the best speed and efficiency.

All three levels

Beginner. A chip designed for one specific job and manufactured that way, so it cannot be rewired later.

Novice. Application-specific integrated circuit: a custom chip fabricated from your own design, with high up-front cost and the best speed and efficiency.

Expert. Fixed function after tapeout, with mask NRE and months of fab and bring-up time. It pays off when the function is stable and either volume or performance margin justifies the cost.

ASIL

Automotive Safety Integrity Level. Hazard analysis rates each hazard by severity, exposure and controllability; the combination gives QM (no safety requirement) or ASIL A to D.

All three levels

Beginner. A rating from A to D for how dangerous a failure would be. D is the strictest.

Novice. Automotive Safety Integrity Level. Hazard analysis rates each hazard by severity, exposure and controllability; the combination gives QM (no safety requirement) or ASIL A to D.

Expert. Drives hardware metric targets (SPFM, LFM, PMHF), methods and independence of confirmation measures. ASIL decomposition can split a requirement across redundant independent elements.

backside power delivery

Moving the power distribution network to the back of the wafer and connecting it up to the transistors with nano-scale vias.

All three levels

Beginner. Feeding power to the chip from underneath, so the wiring on top can be used for signals.

Novice. Moving the power distribution network to the back of the wafer and connecting it up to the transistors with nano-scale vias.

Expert. Separates the PDN from the signal BEOL, cutting IR drop and freeing routing tracks. It changes cell architecture, thermal paths, and failure analysis, since the substrate side is no longer open for probing.

biocompatibility

Evaluation of device materials for adverse biological responses, following ISO 10993-1 within a risk management process.

All three levels

Beginner. Making sure the materials touching the body do not cause harm, such as irritation or toxicity.

Novice. Evaluation of device materials for adverse biological responses, following ISO 10993-1 within a risk management process.

Expert. Drives package materials, coatings, and electrode metals, and any material change can reopen biological evaluation.

chiplet

A die built to be assembled with other dies in a package and connected by short, dense die-to-die links.

All three levels

Beginner. A smaller chip designed to be combined with others inside one package so they act like one big chip.

Novice. A die built to be assembled with other dies in a package and connected by short, dense die-to-die links.

Expert. A die whose interfaces, test, and power assume multi-die integration. Partitioning trades yield and node choice per function against die-to-die power, latency, and package cost.

Clock buffer

A buffer or inverter cell from the library chosen for clock trees (e.g. CLKBUF_X8, CLKINV_X4), usually with matched rise/fall delays and strong drive.

All three levels

Beginner. A small amplifier that re-strengthens the clock signal so it can travel further and feed more parts.

Novice. A buffer or inverter cell from the library chosen for clock trees (e.g. CLKBUF_X8, CLKINV_X4), usually with matched rise/fall delays and strong drive.

Expert. Clock cells trade area and input capacitance for balanced rise/fall, tight delay distributions and EM-robust outputs. Inverter-based trees alternate edge polarity per level, which limits duty-cycle drift.

Clock gating

Replacing flip-flop enable logic with a gate on the clock itself, so a group of flops receives no clock edges when they would hold their value. It cuts dynamic power.

All three levels

Beginner. Switching off the clock to parts of the chip that have nothing to do, like turning off lights in empty rooms.

Novice. Replacing flip-flop enable logic with a gate on the clock itself, so a group of flops receives no clock edges when they would hold their value. It cuts dynamic power.

Expert. Synthesis inserts integrated clock-gating (ICG) cells, latch-based for a glitch-free gated clock, wherever a group of flops shares an enable. Teams set a minimum bank size, check enable timing to the ICG, and tie or connect the ICG’s test-enable pin for scan.

Clock mesh

A grid of shorted clock wires driven by many buffers in parallel, with short local stubs to the flops. Very low skew and variation, high power.

All three levels

Beginner. A grid of clock wires all tied together, so every area of the chip gets the tick from several directions at once.

Novice. A grid of shorted clock wires driven by many buffers in parallel, with short local stubs to the flops. Very low skew and variation, high power.

Expert. Resistances in parallel average out variation and drivers short together, so skew at the fabric is near zero. Costs: wire capacitance, short-circuit current between drivers, and analysis that needs SPICE-class simulation because the network is not a tree.

Clock skew

The difference in clock arrival time between two sinks. On this page skew = capture arrival − launch arrival, so positive skew gives the data path extra time.

All three levels

Beginner. How far apart in time the same clock tick reaches two different parts of the chip.

Novice. The difference in clock arrival time between two sinks. On this page skew = capture arrival − launch arrival, so positive skew gives the data path extra time.

Expert. Global skew is the max−min latency over all sinks; local skew is measured between sequentially adjacent (related) sinks and is what timing actually depends on. Sign conventions differ between textbooks and tools, so always check which arrival is subtracted.

Clock transition (slew)

The rise or fall time of the clock waveform at a pin, usually measured between 10/90% or 20/80% thresholds. CTS enforces a maximum.

All three levels

Beginner. How sharp the clock tick is: a crisp click or a slow fade.

Novice. The rise or fall time of the clock waveform at a pin, usually measured between 10/90% or 20/80% thresholds. CTS enforces a maximum.

Expert. Slow clock slew increases flop clock-to-Q and setup/hold requirements, raises short-circuit power and makes the edge more sensitive to noise. Max-transition limits on clock nets are typically tighter than on data nets.

Clock tree synthesis (CTS)

The physical-design step, run after placement, that inserts and places clock buffers/inverters and builds a distribution network from the clock root to every sink while meeting skew, latency and transition targets.

All three levels

Beginner. The step that builds the network of wires and amplifiers that carries the chip’s heartbeat to every memory cell.

Novice. The physical-design step, run after placement, that inserts and places clock buffers/inverters and builds a distribution network from the clock root to every sink while meeting skew, latency and transition targets.

Expert. Topology construction, buffering, sizing and balancing of each clock network against per-skew-group targets, followed by propagated-clock optimization (CCD/useful skew, hold repair). Commercial: Cadence Innovus CCOpt, Synopsys ICC2/Fusion Compiler; open source: OpenROAD TritonCTS.

Clock uncertainty

An SDC margin (set_clock_uncertainty) subtracted from setup and added to hold checks to cover jitter and, before CTS, expected skew.

All three levels

Beginner. A safety margin for the clock tick wobbling a little from cycle to cycle.

Novice. An SDC margin (set_clock_uncertainty) subtracted from setup and added to hold checks to cover jitter and, before CTS, expected skew.

Expert. Pre-CTS uncertainty = jitter + skew estimate + margin; post-CTS the skew part is removed because propagated clocks capture it. Setup and hold values are set separately, and inter-clock uncertainty covers cross-clock paths.

Common Criteria

ISO/IEC 15408, a framework where products are evaluated against a security target and assigned an Evaluation Assurance Level (EAL).

All three levels

Beginner. An international system for having independent labs check and certify how secure a product is.

Novice. ISO/IEC 15408, a framework where products are evaluated against a security target and assigned an Evaluation Assurance Level (EAL).

Expert. Smart-card ICs are evaluated against a protection profile, typically EAL4 or higher augmented with AVA_VAN.5, meaning resistance to attackers with high attack potential, plus development-site security (ALC_DVS).

Congestion

Routing demand exceeding routing supply in a region. Tools divide the chip into tiles, estimate how many wire tracks each tile needs on each layer, and compare that to how many tracks exist. Over-capacity tiles show up as hot spots on a congestion map.

All three levels

Beginner. A traffic jam of wires: a spot where more wires need to pass than there are lanes to carry them.

Novice. Routing demand exceeding routing supply in a region. Tools divide the chip into tiles, estimate how many wire tracks each tile needs on each layer, and compare that to how many tracks exist. Over-capacity tiles show up as hot spots on a congestion map.

Expert. Measured per GCell and layer as demand vs. capacity, reported as overflow. During placement it is estimated (RUDY, probabilistic models or a quick global route). Causes include high local cell or pin density, macro corners and channels, and high-fanout or high-pin-count cells clustered together.

COTS

Commercial off-the-shelf components, not designed or qualified for radiation.

All three levels

Beginner. Ordinary off-the-shelf parts, like the chips in phones and laptops.

Novice. Commercial off-the-shelf components, not designed or qualified for radiation.

Expert. Better performance, power and cost than rad-hard parts but highly susceptible to radiation; used in small satellites with rad-hard supervisors, ECC, watchdogs and scrubbing around them.

Counterfeit part

A part that is recycled, re-marked, cloned or otherwise misrepresented. It may work at first but fail early or out of spec.

All three levels

Beginner. A fake or recycled chip sold as if it were new and genuine.

Novice. A part that is recycled, re-marked, cloned or otherwise misrepresented. It may work at first but fail early or out of spec.

Expert. Most common for obsolete parts bought from brokers. Countermeasures include authorized-source purchasing, inspection and test, and in-package authentication such as DARPA’s SHIELD dielet.

CPPR / CRPR

Common path (or clock reconvergence) pessimism removal: crediting back the difference between late and early delay on the clock path shared by launch and capture.

All three levels

Beginner. Removing a double-counted safety margin on the part of the clock path that two memory cells share.

Novice. Common path (or clock reconvergence) pessimism removal: crediting back the difference between late and early delay on the clock path shared by launch and capture.

Expert. With OCV the shared segment is late for launch and early for capture in the same check, which is physically impossible. CPPR adds that difference back. Trees that maximize the common path for critical pairs gain slack.

Critical path

The register-to-register (or I/O) path with the worst slack. Its delay limits the maximum clock frequency.

All three levels

Beginner. The slowest route a signal takes through the circuit. It sets how fast the whole chip can run.

Novice. The register-to-register (or I/O) path with the worst slack. Its delay limits the maximum clock frequency.

Expert. The worst-slack path in a path group. Optimizers spend most effort near it (sizing, restructuring, buffering), and area recovery runs on everything else. Fixing one critical path often exposes the next, so look at the whole slack distribution.

Deemed export

Under ITAR, releasing technical data to a foreign person inside the U.S. is treated as an export to that person’s countries of citizenship and residency.

All three levels

Beginner. Showing controlled technology to a foreign citizen counts as exporting it, even if nobody leaves the country.

Novice. Under ITAR, releasing technical data to a foreign person inside the U.S. is treated as an export to that person’s countries of citizenship and residency.

Expert. Drives access control on repositories, EDA servers and design reviews. Mixed-nationality teams need licenses or partitioned data before they touch controlled RTL, netlists or layout.

Density overflow

During global placement, the fraction of cell area sitting in bins that are over the target density. It starts near 1 (everything clumped) and the placer stops when it reaches a target such as 0.1.

All three levels

Beginner. A measure of how much the parts are still piled on top of each other during the rough placement.

Novice. During global placement, the fraction of cell area sitting in bins that are over the target density. It starts near 1 (everything clumped) and the placer stops when it reaches a target such as 0.1.

Expert. Per bin, demand minus capacity; summed over overfull bins and normalized by movable area. The primary convergence metric for Nesterov placers and the trigger for timing-driven reweighting and routability inflation passes.

Detailed placement

Local improvement after legalization: swapping cells, reordering neighbors in a row, flipping orientation, all while staying legal.

All three levels

Beginner. The final polish: small swaps and shuffles of nearby parts that shave off a little more wire.

Novice. Local improvement after legalization: swapping cells, reordering neighbors in a row, flipping orientation, all while staying legal.

Expert. Moves such as global swap, vertical swap, local reordering of small windows, cell mirroring and single-segment clustering. Advanced-node detailed placers also fix cell-adjacency rule violations and pin-access conflicts.

deterministic latency

Latency that does not vary with load, cache state, or interrupts, because every operation takes a fixed number of clock cycles.

All three levels

Beginner. Taking exactly the same amount of time every time, with no surprises.

Novice. Latency that does not vary with load, cache state, or interrupts, because every operation takes a fixed number of clock cycles.

Expert. Achieved by removing queues, caches, arbitration, and shared buses from the critical path. Residual variation comes from clock-domain crossings, SerDes alignment, and off-chip memory.

DICE flip-flop

Dual Interlocked storage Cell: stores each bit on redundant interlocked nodes, so an upset on one node is restored by the others.

All three levels

Beginner. A memory cell built with a backup copy inside it, so one hit can’t flip it.

Novice. Dual Interlocked storage Cell: stores each bit on redundant interlocked nodes, so an upset on one node is restored by the others.

Expert. Cheaper than TMR in area but vulnerable to multi-node charge collection; effectiveness drops at highly scaled nodes, which led to layout-aware variants and node-spacing rules.

DMSMS

Diminishing Manufacturing Sources and Material Shortages: the loss, or coming loss, of manufacturers or suppliers of parts or materials.

All three levels

Beginner. When the companies that make a part stop making it while the system that needs it is still in use.

Novice. Diminishing Manufacturing Sources and Material Shortages: the loss, or coming loss, of manufacturers or suppliers of parts or materials.

Expert. A program-level discipline in DoD. For chips it means lifetime buys, redesign onto a new process, emulation, or portable RTL and documentation that let a part be re-implemented decades later.

DPPM

Defective parts per million: the outgoing quality measure automotive customers track, with a goal of zero.

All three levels

Beginner. How many bad chips slip through out of every million shipped.

Novice. Defective parts per million: the outgoing quality measure automotive customers track, with a goal of zero.

Expert. Driven down by high test coverage, outlier screening such as Part Average Testing, burn-in or stress screens, and design for test and analysis.

DVFS

Dynamic voltage and frequency scaling: changing supply voltage and clock frequency at run time. Dynamic power scales with V²f, so lower operating points save a lot.

All three levels

Beginner. Slowing the chip down and lowering its voltage when there is little work, to save battery.

Novice. Dynamic voltage and frequency scaling: changing supply voltage and clock frequency at run time. Dynamic power scales with V²f, so lower operating points save a lot.

Expert. Requires characterized operating points, voltage regulators, PLL relock or clock switching, and signoff at every supported V/f pair, often per domain.

EAR

Export Administration Regulations (15 CFR 730–774), run by the Commerce Department. Items are classified by ECCN on the Commerce Control List.

All three levels

Beginner. U.S. rules that control exports of technology that has both civilian and military uses.

Novice. Export Administration Regulations (15 CFR 730–774), run by the Commerce Department. Items are classified by ECCN on the Commerce Control List.

Expert. Covers dual-use items and the “600 series” military items moved from the USML; for example, ASICs programmed for 600-series items fall under ECCN 3A611.f. Radiation-hardened ICs above set thresholds are controlled under 3A001.a.1.

EDAC

Error detection and correction: codes such as Hamming SECDED or Reed-Solomon added to memory words.

All three levels

Beginner. Extra check bits stored with data so the chip can spot and fix mistakes.

Novice. Error detection and correction: codes such as Hamming SECDED or Reed-Solomon added to memory words.

Expert. Pair with scrubbing so single errors are corrected before a second hit makes them uncorrectable. Code choice depends on expected multi-bit upset patterns and interleaving.

Elaboration

Turning parsed RTL into a generic circuit: resolving parameters and generate blocks, building the module hierarchy and converting always blocks into operators, multiplexers and registers.

All three levels

Beginner. The step where the tool reads the design description and builds its own internal picture of it.

Novice. Turning parsed RTL into a generic circuit: resolving parameters and generate blocks, building the module hierarchy and converting always blocks into operators, multiplexers and registers.

Expert. The front end of synthesis. It fixes parameter values, unrolls generates, infers flops, latches and memories, and produces a technology-independent word-level netlist. Latch inference and width mismatches surface here, so elaboration warnings deserve review before anything else.

Electrostatic (analytical) placement

Global placement that models cells as positive charges whose repulsion spreads them out, balanced against a smooth wirelength function that pulls connected cells together, and solves the whole thing with gradient-based optimization.

All three levels

Beginner. A way of spreading parts out by treating each one like an electric charge that pushes others away, while wires pull connected parts together.

Novice. Global placement that models cells as positive charges whose repulsion spreads them out, balanced against a smooth wirelength function that pulls connected cells together, and solves the whole thing with gradient-based optimization.

Expert. ePlace’s eDensity: charge = cell area, density penalty = potential energy, field from Poisson’s equation solved by FFT, objective W + λN optimized with Nesterov’s method. Used in RePlAce, OpenROAD gpl and DREAMPlace.

Elmore delay

For an RC tree, the sum over each resistor of its resistance times all capacitance downstream of it. Wire delay grows with the square of length.

All three levels

Beginner. A quick formula for estimating how long a signal takes to travel along a wire.

Novice. For an RC tree, the sum over each resistor of its resistance times all capacitance downstream of it. Wire delay grows with the square of length.

Expert. The first moment of the impulse response: cheap, additive and faithful for ranking choices, but not accurate enough for signoff. Ignores input slew shape and inductance; tools use characterized lookup tables and SPICE-calibrated models instead.

emulation

Mapping RTL onto a hardware emulator or FPGA array so it runs millions of times faster than software simulation.

All three levels

Beginner. Running a chip’s design on special reprogrammable hardware so it behaves like the real chip, only slower.

Novice. Mapping RTL onto a hardware emulator or FPGA array so it runs millions of times faster than software simulation.

Expert. Hardware-accelerated execution of RTL at MHz rates, used for software bring-up, OS boot, and long performance tests. Capacity, compile time, and debug visibility are the limits.

Endcap (boundary) cell

A physical-only cell placed at both ends of each row and around macros so the row edges meet manufacturing rules.

All three levels

Beginner. A cap placed at the start and end of every row, like bookends, to finish the row properly.

Novice. A physical-only cell placed at both ends of each row and around macros so the row edges meet manufacturing rules.

Expert. LEF CLASS ENDCAP PRE/POST. Inserted with taps before placement and FIXED. Advanced nodes add corner and boundary variants for well, implant and poly edges around macros and row ends.

essential performance

In IEC 60601-1, the performance whose loss or degradation would create unacceptable risk.

All three levels

Beginner. The things a medical device must keep doing correctly so that patients are not harmed.

Novice. In IEC 60601-1, the performance whose loss or degradation would create unacceptable risk.

Expert. Identified through risk management and used to define test pass criteria, for example that EMC disturbances must not cause unintended or unsafe stimulation.

False path

An SDC exception (set_false_path) that removes a path from timing analysis, for example between unrelated clock domains.

All three levels

Beginner. A route the tool is told to ignore for timing because signals never really need to make it in one clock tick.

Novice. An SDC exception (set_false_path) that removes a path from timing analysis, for example between unrelated clock domains.

Expert. A blunt exception: the path is neither optimized nor checked. Use it only where a synchronizer or protocol makes timing irrelevant, scope it narrowly, and review it, because a wrong false path hides a real bug until silicon.

Fault injection

Inserting faults (stuck-at, bit flips, transients) into RTL or gate-level simulation and seeing whether they reach outputs and whether a safety mechanism detects them.

All three levels

Beginner. Breaking a design on purpose, in simulation, to check that its safety checks work.

Novice. Inserting faults (stuck-at, bit flips, transients) into RTL or gate-level simulation and seeing whether they reach outputs and whether a safety mechanism detects them.

Expert. Classifies faults as observed/not observed at outputs and detected/not detected at error signals; dangerous undetected faults reduce SPFM. Campaigns are expensive and are accelerated with fault-list pruning and formal analysis.

FDA device class

Class I (lowest risk), Class II, and Class III (highest risk). Class III devices such as most implants generally need premarket approval (PMA).

All three levels

Beginner. The risk level the U.S. regulator assigns a medical device. Higher risk means more proof is needed before it can be sold.

Novice. Class I (lowest risk), Class II, and Class III (highest risk). Class III devices such as most implants generally need premarket approval (PMA).

Expert. Class sets the controls and pathway: general controls, special controls, and 510(k) for most Class I/II devices; PMA for Class III. Post-approval changes then follow the same pathway’s change rules.

FMEDA

Failure Modes, Effects and Diagnostic Analysis: lists failure modes per block with failure rates, effects on safety goals, and the diagnostic coverage of safety mechanisms.

All three levels

Beginner. A detailed table of every way each part of the chip could fail and whether something would catch it.

Novice. Failure Modes, Effects and Diagnostic Analysis: lists failure modes per block with failure rates, effects on safety goals, and the diagnostic coverage of safety mechanisms.

Expert. The quantitative backbone of the hardware safety case; produces SPFM, LFM and PMHF. Its coverage numbers should be validated by fault injection.

FPGA

Field-programmable gate array: a grid of configurable logic blocks and routing loaded with a bitstream, so the function can change without making a new chip.

All three levels

Beginner. A chip whose wiring can be reprogrammed after it is built.

Novice. Field-programmable gate array: a grid of configurable logic blocks and routing loaded with a bitstream, so the function can change without making a new chip.

Expert. No mask NRE and in-field updates, at a cost in power, area and speed against an ASIC. For defense, the device is a commercial part with its own supply chain, and the bitstream becomes the asset to protect.

Functional safety

Absence of unreasonable risk from malfunctioning electrical/electronic systems. For cars it is defined by ISO 26262.

All three levels

Beginner. Making sure that when electronics fail, they fail in a way that doesn’t hurt anyone.

Novice. Absence of unreasonable risk from malfunctioning electrical/electronic systems. For cars it is defined by ISO 26262.

Expert. Covers random hardware faults (quantified by architectural metrics and PMHF) and systematic faults (controlled by process). Perception and intended-function shortfalls fall under ISO 21448 (SOTIF).

Global placement

The step that finds approximate cell locations minimizing wirelength while keeping density below a target in every bin. Cells may overlap slightly and are not yet aligned to sites.

All three levels

Beginner. The first, rough pass that decides roughly where every part should go, even if a few parts still overlap.

Novice. The step that finds approximate cell locations minimizing wirelength while keeping density below a target in every bin. Cells may overlap slightly and are not yet aligned to sites.

Expert. A continuous optimization over (x, y) with a density constraint relaxed into a penalty. Modern engines are analytical: quadratic (SimPL, ComPLx) or nonlinear electrostatic (ePlace, RePlAce, DREAMPlace). It ends when density overflow falls below a target such as 10%.

H-tree

A recursive symmetric clock topology where each branch splits into two equal-length branches, giving equal path length to all leaves.

All three levels

Beginner. A symmetric branching pattern shaped like nested letter H’s, so every endpoint is the same distance from the center.

Novice. A recursive symmetric clock topology where each branch splits into two equal-length branches, giving equal path length to all leaves.

Expert. Exact zero skew by symmetry for uniform loads, so it is used for the top levels of distribution. Blockages and non-uniform sinks break the symmetry, and its wirelength and capacitance exceed a sink-driven tree’s.

Halo (keep-out margin)

A placement blockage attached to a macro that extends a set distance from each of its edges and moves with it.

All three levels

Beginner. A clear border kept around a big block so small parts don’t crowd right up against it.

Novice. A placement blockage attached to a macro that extends a set distance from each of its edges and moves with it.

Expert. DEF COMPONENTS + HALO [SOFT] left bottom right top. Gives the router room to reach macro pins and reduces congestion and pin-access trouble at macro edges. A soft halo is honored only during initial placement.

Hardware Trojan

A malicious modification to a circuit, usually a rare-event trigger plus a payload that leaks data, changes function or disables the chip.

All three levels

Beginner. A hidden, harmful change to a chip that stays quiet until something triggers it.

Novice. A malicious modification to a circuit, usually a rare-event trigger plus a payload that leaks data, changes function or disables the chip.

Expert. Can enter through RTL, third-party IP, EDA tools, the foundry or packaging. Small triggers evade functional test; detection combines logic testing for rare conditions, side-channel analysis and physical reverse engineering.

HBM (High Bandwidth Memory)

Stacked DRAM dies connected by through-silicon vias, linked to the processor by a very wide interface through an interposer.

All three levels

Beginner. Memory chips stacked on top of each other and placed right next to the processor, with thousands of connections for very fast data flow.

Novice. Stacked DRAM dies connected by through-silicon vias, linked to the processor by a very wide interface through an interposer.

Expert. JEDEC stacked DRAM with a 1,024-bit (HBM3) or 2,048-bit (HBM4) interface per stack. PHY placement, interposer routing, and thermal coupling between logic and DRAM constrain the floorplan.

HDE (Humanitarian Device Exemption)

An FDA pathway for humanitarian use devices that exempts them from the effectiveness requirement, while still requiring safety and probable benefit.

All three levels

Beginner. A special U.S. approval route for devices that help small groups of patients with rare conditions.

Novice. An FDA pathway for humanitarian use devices that exempts them from the effectiveness requirement, while still requiring safety and probable benefit.

Expert. Approval rests on reasonable assurance of safety and probable benefit, documented in a public Summary of Safety and Probable Benefit.

hermetic package

A sealed enclosure, often titanium or ceramic with brazed feedthroughs, that blocks moisture from reaching the implant’s circuits.

All three levels

Beginner. A sealed metal or ceramic case that keeps body fluids away from the electronics.

Novice. A sealed enclosure, often titanium or ceramic with brazed feedthroughs, that blocks moisture from reaching the implant’s circuits.

Expert. Qualified by leak and internal water vapor tests, corrosion soak tests, and environmental stress. Feedthrough count limits how many electrodes the ASIC can drive.

Hold time

The minimum time data must stay stable after the capturing edge. Hold check: launch arrival + data delay ≥ capture arrival + hold. The period does not appear.

All three levels

Beginner. How long the data must stay unchanged after the clock tick so the memory cell isn’t confused.

Novice. The minimum time data must stay stable after the capturing edge. Hold check: launch arrival + data delay ≥ capture arrival + hold. The period does not appear.

Expert. Hold uses early data and late capture clock. Because frequency cannot fix it, a hold violation in silicon is fatal at any speed. Most hold buffers are added right after CTS, once real skew is known.

HPWL (half-perimeter wirelength)

For each net, the width plus the height of the bounding box of its pins. Summed over all nets, it is the standard placement objective because it is cheap to compute and tracks routed wirelength well.

All three levels

Beginner. A quick way to guess how much wire a connection needs: draw the smallest box around all the parts it connects and add the box’s width and height.

Novice. For each net, the width plus the height of the bounding box of its pins. Summed over all nets, it is the standard placement objective because it is cheap to compute and tracks routed wirelength well.

Expert. Exact for two-pin nets and a lower bound on the rectilinear Steiner tree for larger nets. It is not differentiable (it is built from max and min), so analytical placers optimize smooth surrogates such as log-sum-exp or weighted-average and report true HPWL.

HSM

Hardware security module: a tamper-resistant device that generates, stores, and uses keys without exposing them to the host.

All three levels

Beginner. A locked box of hardware that banks use to store and use their most important cryptographic keys.

Novice. Hardware security module: a tamper-resistant device that generates, stores, and uses keys without exposing them to the host.

Expert. Usually validated to FIPS 140-3. Built from secure processors, crypto accelerators, and tamper detection that zeroizes keys on intrusion.

hybrid bonding

A direct copper-to-copper and oxide-to-oxide bond between stacked dies or wafers, with pitches far finer than solder microbumps.

All three levels

Beginner. A way to join two chips face to face, copper to copper, so they connect at millions of points without solder.

Novice. A direct copper-to-copper and oxide-to-oxide bond between stacked dies or wafers, with pitches far finer than solder microbumps.

Expert. Bumpless Cu/dielectric bonding with pitches from several micrometers down to sub-micrometer in research. It needs extreme surface planarity and cleanliness and makes known-good-die test and thermal design harder.

Ideal clock

A clock modeled with zero (or user-estimated) network delay and a user-specified transition. Synthesis and placement time against ideal clocks.

All three levels

Beginner. A pretend clock that reaches everything instantly, used before the real wiring exists.

Novice. A clock modeled with zero (or user-estimated) network delay and a user-specified transition. Synthesis and placement time against ideal clocks.

Expert. In ideal mode set_clock_latency, set_clock_transition and a larger set_clock_uncertainty stand in for the tree. Forgetting to remove those after CTS double-counts the tree.

implantable device

An active medical device surgically placed in the body, powered by a primary battery, a rechargeable battery, or a wireless link.

All three levels

Beginner. A medical device placed inside the body, such as a pacemaker, and left there for years.

Novice. An active medical device surgically placed in the body, powered by a primary battery, a rechargeable battery, or a wireless link.

Expert. A device whose electronics sit in a hermetic package exposed to body temperature and fluids for its whole life. Replacement means surgery, so battery life and reliability dominate the design.

Insertion delay (clock latency)

Delay from the clock source to a sink’s clock pin. Source latency is outside the clock definition point; network latency is the on-chip tree.

All three levels

Beginner. How long the clock tick takes to travel from where it enters the chip to a memory cell.

Novice. Delay from the clock source to a sink’s clock pin. Source latency is outside the clock definition point; network latency is the on-chip tree.

Expert. Latency matters beyond skew: longer uncommon latency means more delay exposed to OCV derates, more jitter accumulation, more power. Pre-CTS it is modeled with set_clock_latency; post-CTS the tool propagates real delays.

IR drop

Voltage lost across the resistance of the power grid (current × resistance). Too much drop slows gates or breaks timing.

All three levels

Beginner. The small loss of voltage as power travels through thin wires to reach each part of the chip.

Novice. Voltage lost across the resistance of the power grid (current × resistance). Too much drop slows gates or breaks timing.

Expert. Static and dynamic voltage droop across the PDN; dynamic droop from simultaneous switching is the harder case and must be signed off together with timing.

isolation cell

A cell that clamps a power-gated domain’s output to a known value so floating signals do not corrupt powered-on logic.

All three levels

Beginner. A gate that holds a signal steady when the part of the chip that drives it is switched off.

Novice. A cell that clamps a power-gated domain’s output to a known value so floating signals do not corrupt powered-on logic.

Expert. Placed per UPF on domain crossings and powered from the receiving or always-on supply. Its enable must be asserted before power-down and released after power-up.

ITAR

International Traffic in Arms Regulations (22 CFR 120–130). Items on the U.S. Munitions List, and the technical data that describe them, need State Department authorization to export.

All three levels

Beginner. U.S. rules that control who can receive weapons technology, including the designs for some chips.

Novice. International Traffic in Arms Regulations (22 CFR 120–130). Items on the U.S. Munitions List, and the technical data that describe them, need State Department authorization to export.

Expert. USML Category XI(c)(1) covers ASICs and PLDs programmed for defense articles, so design databases for such parts are technical data. Releasing them to a foreign person, even inside the U.S., is an export.

known-good die

A bare die tested well enough before assembly that it is unlikely to cause a multi-die package to fail.

All three levels

Beginner. A chip that has been fully tested before it is packaged with other chips.

Novice. A bare die tested well enough before assembly that it is unlikely to cause a multi-die package to fail.

Expert. Wafer-level test coverage high enough to keep package-level yield acceptable; it pushes at-speed and die-to-die interface test to wafer sort.

Latent fault metric (LFM)

Coverage of multiple-point faults that would otherwise stay undetected. Targets: ≥60% for ASIL B, ≥80% for C, ≥90% for D.

All three levels

Beginner. How well the chip finds hidden faults that do no harm alone but could combine with a second fault.

Novice. Coverage of multiple-point faults that would otherwise stay undetected. Targets: ≥60% for ASIL B, ≥80% for C, ≥90% for D.

Expert. Latent faults often sit in the safety mechanisms themselves; LBIST, MBIST and mechanism self-checks raise LFM.

LBIST

Logic built-in self-test: on-chip pattern generation applied through scan chains, with a signature compared to an expected value.

All three levels

Beginner. A self-test the chip can run on its own logic, without outside test equipment.

Novice. Logic built-in self-test: on-chip pattern generation applied through scan chains, with a signature compared to an expected value.

Expert. Used in the field to detect latent faults; the run must fit the diagnostic test interval and power budget, and functional state must be saved or restored around it.

Legalization

Moving each cell from its global-placement position to the nearest legal site in a row, with no overlaps and no cells on blockages, while minimizing total displacement.

All three levels

Beginner. Snapping every part into a proper slot in a row so nothing overlaps, while moving each part as little as possible.

Novice. Moving each cell from its global-placement position to the nearest legal site in a row, with no overlaps and no cells on blockages, while minimizing total displacement.

Expert. Greedy (Tetris), row-based dynamic (Abacus), flow-based, diffusion and negotiation-based methods. Must also respect fences, padding, edge-spacing rules and multi-height rail alignment. Large displacement here destroys the wirelength and timing that global placement achieved.

Liberty (.lib)

A text file format describing a standard-cell library: each cell’s logic function, area, pin capacitances, delay tables and power. Synthesis and timing tools read it.

All three levels

Beginner. The catalog that tells the tool each building block’s size, speed and power use.

Novice. A text file format describing a standard-cell library: each cell’s logic function, area, pin capacitances, delay tables and power. Synthesis and timing tools read it.

Expert. One Liberty file per PVT corner (and often per Vt flavor). It holds NLDM or current-source timing and power tables, timing checks (setup, hold), design-rule limits (max_transition, max_capacitance) and, in older flows, wire-load models. Synthesis results are only as good as the corner and library set you load.

Lockstep

Dual-core lockstep (DCLS) runs the same software on two cores and compares outputs; a mismatch flags a fault.

All three levels

Beginner. Two identical processors run the same program and constantly compare answers.

Novice. Dual-core lockstep (DCLS) runs the same software on two cores and compares outputs; a mismatch flags a fault.

Expert. A small time stagger between cores means a common-cause disturbance produces different errors, so comparison detects it. Standard for ASIL D control functions.

Logic depth

The number of gate levels on the longest input-to-output path. It is a rough first estimate of delay.

All three levels

Beginner. How many building blocks a signal passes through, one after another, from input to output.

Novice. The number of gate levels on the longest input-to-output path. It is a rough first estimate of delay.

Expert. Levels of logic on a path, in AIG nodes or mapped gates. It tracks delay only loosely because real delay depends on gate type, load, slew and wires; it is still the quantity that balancing and depth-oriented mapping minimize.

Logic locking

Inserting key-controlled gates (for example XOR/XNOR) into a netlist. Only the correct key, loaded after manufacture, restores correct behavior.

All three levels

Beginner. Building a secret key into a chip so a stolen copy computes wrong answers without it.

Novice. Inserting key-controlled gates (for example XOR/XNOR) into a netlist. Only the correct key, loaded after manufacture, restores correct behavior.

Expert. Aimed at overproduction and IP piracy by an untrusted foundry. The SAT attack recovers keys using an unlocked chip as an oracle; most later schemes trade resistance to it against other attacks and overhead.

Logical equivalence checking (LEC)

Formal verification that two representations of a design (for example RTL and the synthesized netlist) compute the same outputs for all inputs, without running test vectors.

All three levels

Beginner. A mathematical check that the finished parts list does exactly what the original design said, for every possible input.

Novice. Formal verification that two representations of a design (for example RTL and the synthesized netlist) compute the same outputs for all inputs, without running test vectors.

Expert. Matches state points (flops, ports, black boxes) between reference and implementation, then proves each matched combinational cone equal using AIGs, simulation, SAT and BDDs. Retiming, FSM recoding and merged or removed registers need guidance or sequential checking.

MAC (multiply-accumulate)

The operation a ← a + b × c. Accelerators count their peak throughput in MACs per cycle.

All three levels

Beginner. One multiplication added onto a running total. Neural networks need billions of them.

Novice. The operation a ← a + b × c. Accelerators count their peak throughput in MACs per cycle.

Expert. The basic datapath cell of matrix engines. Its precision (INT8, FP8, BF16) sets area and energy per operation, and accumulator width sets numerical headroom.

MedRadio / MICS

The FCC’s Medical Device Radiocommunication Service. Its 402–405 MHz core band began as the Medical Implant Communication Service (MICS) in 1999.

All three levels

Beginner. Radio frequencies set aside for medical implants to talk to outside equipment.

Novice. The FCC’s Medical Device Radiocommunication Service. Its 402–405 MHz core band began as the Medical Implant Communication Service (MICS) in 1999.

Expert. Ultra-low-power, non-voice service with tight EIRP limits and frequency-monitoring rules. Implant radios must also coexist with inductive links and survive tissue attenuation within a µA-level average current budget.

multi-Vt

Libraries of the same cells built with different transistor threshold voltages. Low-Vt is fast and leaky, high-Vt is slow with low leakage.

All three levels

Beginner. Using a mix of fast-but-leaky and slow-but-frugal transistors, choosing the right kind for each spot.

Novice. Libraries of the same cells built with different transistor threshold voltages. Low-Vt is fast and leaky, high-Vt is slow with low leakage.

Expert. Synthesis and leakage recovery assign Vt flavors per cell under timing constraints. The mix shifts with corner and temperature, so leakage is signed off hot.

Multibit flip-flop

A library cell holding two, four or more flip-flops that share one clock input and internal clock buffering.

All three levels

Beginner. Several one-bit memory cells packed into one block so they can share the clock wiring.

Novice. A library cell holding two, four or more flip-flops that share one clock input and internal clock buffering.

Expert. Banking single-bit flops into multibit cells reduces clock-pin capacitance and clock-tree power and can save area. It is done in synthesis when the library offers the cells and the bits are related, or at placement when physical proximity is known.

Multicycle path

An SDC exception (set_multicycle_path) that gives a path N clock cycles instead of one, used when the design only samples the result every N cycles.

All three levels

Beginner. A route that is allowed more than one clock tick to finish.

Novice. An SDC exception (set_multicycle_path) that gives a path N clock cycles instead of one, used when the design only samples the result every N cycles.

Expert. Moves the setup capture edge by N cycles. In standard SDC semantics the default hold check moves with it, so a setup multiplier of N is normally paired with a hold multiplier of N−1 to put the hold check back.

near-threshold computing

Operating with supply voltage close to the transistor threshold voltage, roughly 400–500 mV in the cited study, to cut energy per operation.

All three levels

Beginner. Running the chip at a supply voltage just barely high enough for the transistors to switch, which saves a lot of energy but makes it slower.

Novice. Operating with supply voltage close to the transistor threshold voltage, roughly 400–500 mV in the cited study, to cut energy per operation.

Expert. Energy per op falls steeply toward Vth, but delay and its sensitivity to process, voltage, and temperature variation rise sharply. Needs variation-aware timing, SRAM assist or alternative bitcells, and robust level shifting.

Netlist

A structural description of a circuit as instances of cells plus the nets (wires) that join their pins. After synthesis it is usually written as gate-level Verilog.

All three levels

Beginner. A list of every part in a circuit and which parts connect to which, like a wiring list for a model kit.

Novice. A structural description of a circuit as instances of cells plus the nets (wires) that join their pins. After synthesis it is usually written as gate-level Verilog.

Expert. The gate-level Verilog that carries the design from synthesis through DFT, place-and-route and signoff. Every later stage edits it (scan stitching, buffering, sizing, clock tree), and LEC re-proves it against the RTL after each major change.

NLDM (non-linear delay model)

Liberty’s lookup-table delay model: two-dimensional tables of delay and output transition indexed by input transition time and output load capacitance, interpolated by the tool.

All three levels

Beginner. A small table that tells how slow a building block is, depending on how sharp its input signal is and how much it has to drive.

Novice. Liberty’s lookup-table delay model: two-dimensional tables of delay and output transition indexed by input transition time and output load capacitance, interpolated by the tool.

Expert. Tables characterized from SPICE at fixed slew/load points. Tools interpolate, and extrapolate outside the grid at reduced accuracy. At advanced nodes, current-source models (CCS, ECSM) often supplement NLDM, but synthesis still runs well on NLDM views.

Non-default routing rule (NDR)

A routing rule that overrides the default width/spacing for selected nets, typically double width and/or double spacing for clock nets.

All three levels

Beginner. Special, roomier wiring rules used for the clock so it stays fast and quiet.

Novice. A routing rule that overrides the default width/spacing for selected nets, typically double width and/or double spacing for clock nets.

Expert. Double spacing cuts coupling capacitance and crosstalk delta-delay; double width cuts resistance and helps EM. Applied to trunk and upper levels; leaf nets often stay default to save tracks.

NPU

Neural processing unit: an on-chip accelerator for neural-network inference, usually built around MAC arrays and local SRAM.

All three levels

Beginner. A part of a phone chip specialized for running AI tasks such as recognizing faces or speech.

Novice. Neural processing unit: an on-chip accelerator for neural-network inference, usually built around MAC arrays and local SRAM.

Expert. Sized for perf/W within a tight area budget. It often has its own power domain and DVFS, and its SRAM is a major leakage contributor.

NRE

Non-recurring engineering: design labor, IP, tools, and mask sets, paid once regardless of volume.

All three levels

Beginner. The one-time cost of creating a new chip, paid before the first unit is made.

Novice. Non-recurring engineering: design labor, IP, tools, and mask sets, paid once regardless of volume.

Expert. Amortized across units, so it sets the volume at which an ASIC beats an FPGA. Mask cost rises steeply at advanced nodes.

On-chip variation (OCV)

Within-die variation in delay, modeled in STA by derating early and late paths differently (e.g. late ×1.05, early ×0.95).

All three levels

Beginner. Tiny manufacturing differences that make identical parts on the same chip run at slightly different speeds.

Novice. Within-die variation in delay, modeled in STA by derating early and late paths differently (e.g. late ×1.05, early ×0.95).

Expert. Flat derates, AOCV (derates by logic depth and distance) and POCV/LVF (per-cell sigma, statistically combined). Clock paths are derated too, which is why a long uncommon clock path costs slack.

One-hot encoding

An FSM state encoding with one flip-flop per state, exactly one of which is 1. It uses more flops than binary encoding but usually needs simpler next-state logic.

All three levels

Beginner. A way to label the steps of a machine by giving each step its own on/off switch.

Novice. An FSM state encoding with one flip-flop per state, exactly one of which is 1. It uses more flops than binary encoding but usually needs simpler next-state logic.

Expert. One of several FSM encodings (binary, Gray, one-hot) a synthesis tool may choose after extracting a state machine. Recoding changes the register set, which equivalence checkers must be told about or handle sequentially.

Pin access

The ability of the detailed router to connect to a cell’s pins legally. Dense placement and neighboring pins can block each other’s access points.

All three levels

Beginner. Whether the router can actually reach each pin of a part without breaking a rule.

Novice. The ability of the detailed router to connect to a cell’s pins legally. Dense placement and neighboring pins can block each other’s access points.

Expert. At advanced nodes, tiny M1/M0 pins, few tracks per cell and complex via rules mean that two legal neighbors can still leave a pin unreachable. Placers address this with padding, pin-access-aware detailed placement, and refinement during routing.

Placement blockage

A region where standard cells may not be placed. Hard blockages forbid all cells. Soft blockages keep initial placement out but let later optimization (buffers, clock tree) use the space. Partial blockages cap cell density at a percentage.

All three levels

Beginner. An area marked “no parts here” (or “only a few parts here”) so space stays free for wires or for later use.

Novice. A region where standard cells may not be placed. Hard blockages forbid all cells. Soft blockages keep initial placement out but let later optimization (buffers, clock tree) use the space. Partial blockages cap cell density at a percentage.

Expert. In DEF: BLOCKAGES with PLACEMENT, PLACEMENT + SOFT, or PLACEMENT + PARTIAL maxDensity. Typical uses: macro channels, notches, areas over sensitive analog, and partial blockages over predicted congestion hot spots.

PMA (premarket approval)

FDA’s review pathway for Class III devices, requiring evidence of safety and effectiveness before sale.

All three levels

Beginner. The strictest U.S. approval process for medical devices, used for the highest-risk ones.

Novice. FDA’s review pathway for Class III devices, requiring evidence of safety and effectiveness before sale.

Expert. After approval, changes affecting safety or effectiveness, including circuit, component, layout, and manufacturing-site changes, require an approved PMA supplement before implementation.

PMHF

Probabilistic Metric for random Hardware Failures, in FIT (failures per 10⁹ hours). Targets: under 100 FIT for ASIL B and C, under 10 FIT for D.

All three levels

Beginner. A number for how often random hardware failures could break a safety goal.

Novice. Probabilistic Metric for random Hardware Failures, in FIT (failures per 10⁹ hours). Targets: under 100 FIT for ASIL B and C, under 10 FIT for D.

Expert. Budgeted across the item; an SoC typically gets a fraction, so silicon base failure rates, package and transient (soft-error) rates all count.

power gating

Disconnecting a block from its supply with a header or footer transistor switch so it stops leaking current while idle.

All three levels

Beginner. Cutting off electricity to a part of the chip that is not being used, like switching off the lights in an empty room.

Novice. Disconnecting a block from its supply with a header or footer transistor switch so it stops leaking current while idle.

Expert. Switch networks between the global and virtual rails, controlled by a power-management unit. It requires isolation, retention or state reload, in-rush control, and power-aware verification.

PPA (power, performance, area)

Power, performance (clock frequency or slack) and area: the main quality measures of a synthesized design. Improving one usually costs another.

All three levels

Beginner. The three things every chip trades off: how much power it uses, how fast it runs and how big it is.

Novice. Power, performance (clock frequency or slack) and area: the main quality measures of a synthesized design. Improving one usually costs another.

Expert. The joint objective of implementation. Synthesis explores it through constraints (period, uncertainty), effort settings, library choices (Vt mix, dont_use) and transformations such as retiming, clock gating and resource sharing. Synthesis PPA is an estimate; post-route PPA is what ships.

Propagated clock

A clock whose arrival at each sink is computed from the actual gate and wire delays of the clock network (set_propagated_clock).

All three levels

Beginner. The clock as it really behaves after the tree is built, with real travel delays.

Novice. A clock whose arrival at each sink is computed from the actual gate and wire delays of the clock network (set_propagated_clock).

Expert. Once propagated, every sink has its own latency and slew, OCV derates apply to clock cells, and CPPR becomes meaningful. All post-CTS optimization and signoff uses propagated clocks.

PTP (IEEE 1588)

The Precision Time Protocol: devices exchange timestamped packets to measure and correct clock offset and network delay.

All three levels

Beginner. A way for computers on a network to agree on the exact time, down to tiny fractions of a second.

Novice. The Precision Time Protocol: devices exchange timestamped packets to measure and correct clock offset and network delay.

Expert. Accuracy depends on hardware timestamping at the PHY or MAC, symmetric paths, and boundary or transparent clocks in switches. Sub-nanosecond transfer is possible with optimal network design.

QML (Qualified Manufacturers List)

The MIL-PRF-38535 system in which manufacturers qualify their flows; class Q is the military level and class V is the space level.

All three levels

Beginner. A government list of factories and parts approved for military and space use.

Novice. The MIL-PRF-38535 system in which manufacturers qualify their flows; class Q is the military level and class V is the space level.

Expert. Administered by DLA Land and Maritime, with NASA/JPL and the Aerospace Corporation in the qualifying activity for space parts. Qualification covers electrical, environmental, life, package and radiation groups.

Radiation hardening by design (RHBD)

Hardening through cell design, layout and redundancy in a commercial process, instead of a special radiation-hardened process.

All three levels

Beginner. Making a chip tough against radiation through clever circuit design, using a normal factory.

Novice. Hardening through cell design, layout and redundancy in a commercial process, instead of a special radiation-hardened process.

Expert. Includes hardened standard-cell libraries (DICE, TMR flip-flops, SET filters), layout measures (guard rings, well contacts, node spacing) and architectural redundancy, applied selectively to sensitive cells to limit area and power cost.

Region, guide and fence

A rectangle (or set of rectangles) assigned to a group of cells. A guide is a preference; a fence is a hard rule that also keeps everything else out.

All three levels

Beginner. A fenced yard on the chip where one group of parts must stay together.

Novice. A rectangle (or set of rectangles) assigned to a group of cells. A guide is a preference; a fence is a hard rule that also keeps everything else out.

Expert. DEF REGIONS with TYPE GUIDE or FENCE, and COMPONENTS + REGION. Used for voltage areas, hierarchical blocks and timing-critical clusters. Over-tight fences push local density up and starve the optimizer of space.

Resource sharing

Implementing two mutually exclusive operations (for example two additions in different branches of an if) with one operator and a multiplexer.

All three levels

Beginner. Using one piece of hardware for two jobs that never happen at the same time.

Novice. Implementing two mutually exclusive operations (for example two additions in different branches of an if) with one operator and a multiplexer.

Expert. Merges mutually exclusive arithmetic or other large operators. It saves area but adds mux delay on the shared operator’s inputs, so timing-driven tools weigh it against slack. Yosys proves exclusivity with a SAT solver.

retention flip-flop

A flip-flop with a shadow latch on an always-on supply that saves state before power-down and restores it after.

All three levels

Beginner. A memory bit with a tiny backup that keeps its value while the rest of the block sleeps.

Novice. A flip-flop with a shadow latch on an always-on supply that saves state before power-down and restores it after.

Expert. Trades area and leakage for fast wake-up without software state restore. Save/restore sequencing and the always-on supply routing must be verified.

reticle limit

The maximum exposure field of a lithography scanner, roughly 800 to 860 mm². A monolithic die must fit inside it.

All three levels

Beginner. The largest area a chipmaking machine can print in one shot. A single chip cannot be bigger than this.

Novice. The maximum exposure field of a lithography scanner, roughly 800 to 860 mm². A monolithic die must fit inside it.

Expert. Set by the scanner field (26 mm × 33 mm on current tools). Dies near the limit suffer low yield and few candidates per wafer; going beyond it needs stitching, chiplets, or wafer-scale integration.

Retiming

Moving registers across combinational logic without changing the circuit’s cycle-by-cycle input/output behavior, to balance delay between pipeline stages.

All three levels

Beginner. Moving the circuit’s memory points (flip-flops) a little earlier or later so the work between them is shared out more evenly.

Novice. Moving registers across combinational logic without changing the circuit’s cycle-by-cycle input/output behavior, to balance delay between pipeline stages.

Expert. A sequential transformation formalized by Leiserson and Saxe. It can minimize clock period or register count. It breaks one-to-one register correspondence with the RTL, so equivalence checking needs sequential techniques or tool-generated guidance.

Row and site

The core area is tiled with horizontal rows, each one cell tall and divided into sites (the minimum placement width). Every standard cell must start on a site boundary inside a row. Rows usually alternate orientation (N, FS) so neighboring rows share power rails.

All three levels

Beginner. The neat lanes on the chip where the small building blocks must sit, divided into equal slots like spaces in a parking lot.

Novice. The core area is tiled with horizontal rows, each one cell tall and divided into sites (the minimum placement width). Every standard cell must start on a site boundary inside a row. Rows usually alternate orientation (N, FS) so neighboring rows share power rails.

Expert. Defined by LEF SITE (size, symmetry) and DEF ROW statements (origin, orientation, DO count BY 1 STEP pitch). Multi-height cells span rows and must match rail polarity, which constrains which rows and orientations are legal.

RUDY

Rectangular Uniform wire DensitY: each net’s estimated wire (its HPWL) is spread evenly over its bounding box, and the contributions of all nets are summed per tile to make a congestion map.

All three levels

Beginner. A quick way to guess where wires will pile up, by spreading each connection’s wire evenly over the box around it.

Novice. Rectangular Uniform wire DensitY: each net’s estimated wire (its HPWL) is spread evenly over its bounding box, and the contributions of all nets are summed per tile to make a congestion map.

Expert. Per net, density (w + h)/(w·h) over the bounding box. Router-independent and cheap, so placers call it inside the loop (OpenROAD gpl uses it for cell inflation). It ignores layer assignment and detours, so confirm with a global route.

Safety island

A dedicated, independently protected subsystem (often lockstep cores plus watchdogs) that monitors and manages high-performance compute blocks.

All three levels

Beginner. A small, highly reliable helper inside a big chip that watches the rest and steps in if something goes wrong.

Novice. A dedicated, independently protected subsystem (often lockstep cores plus watchdogs) that monitors and manages high-performance compute blocks.

Expert. Provides watchdogs, fault collection, diagnostics and safe-state control with independence from the monitored domain (separate clock and power where possible).

Safety mechanism

Hardware or software that detects or controls faults and moves the system to a safe state, such as ECC, lockstep comparison or a watchdog.

All three levels

Beginner. A built-in checker that notices when something has gone wrong and reacts.

Novice. Hardware or software that detects or controls faults and moves the system to a safe state, such as ECC, lockstep comparison or a watchdog.

Expert. Credited in the FMEDA with a diagnostic coverage per failure mode; must itself be tested (often by BIST or periodic checks) or its failure becomes a latent fault.

Scan-chain reordering

After placement, the order of flip-flops in each scan chain is changed to shorten the scan wires. Test still works because the order of flops in a shift chain does not change the chip’s function.

All three levels

Beginner. Re-linking the chip’s test chain so each link connects to a nearby neighbor instead of something far away.

Novice. After placement, the order of flip-flops in each scan chain is changed to shorten the scan wires. Test still works because the order of flops in a shift chain does not change the chip’s function.

Expert. Driven by the DEF SCANCHAINS section: FLOATING lists may be reordered, ORDERED lists may not. Cast as a TSP over flop locations, constrained by chain partitions, clock domains and lockup latches. ATPG patterns must be regenerated against the reordered chain.

Scrubbing

Background reads of memory (or FPGA configuration) that correct errors with EDAC and write back clean data.

All three levels

Beginner. Regularly re-reading memory and fixing any errors found, before they pile up.

Novice. Background reads of memory (or FPGA configuration) that correct errors with EDAC and write back clean data.

Expert. The scrub interval is set against the upset rate so the probability of two errors in one code word stays acceptably low.

SDC (timing constraints)

Synopsys Design Constraints: a Tcl-based format with commands such as create_clock, set_input_delay and set_output_delay that define the timing the design must meet.

All three levels

Beginner. Instructions that tell the tool how fast the chip must run and how much time signals have to travel.

Novice. Synopsys Design Constraints: a Tcl-based format with commands such as create_clock, set_input_delay and set_output_delay that define the timing the design must meet.

Expert. The de facto constraint language read by synthesis, STA and place-and-route tools. It defines clocks, I/O budgets, exceptions (false paths, multicycles), uncertainty and design-rule limits. Constraint bugs cause more silicon timing failures than tool bugs, so SDC gets its own review and linting.

secure element

A tamper-resistant microcontroller with crypto engines and sensors that stores keys and runs sensitive operations.

All three levels

Beginner. A small chip, like the one on a payment card, built to keep secret keys safe even if someone steals it.

Novice. A tamper-resistant microcontroller with crypto engines and sensors that stores keys and runs sensitive operations.

Expert. Designed against an attacker with physical access: probing, fault injection, and side channels. Certified against protection profiles at high attack potential.

secure enclave

An isolated security subsystem inside an SoC with its own processor, memory protection, and crypto engines.

All three levels

Beginner. A walled-off section of the chip that guards secrets like fingerprints and payment keys, even from the phone’s main processor.

Novice. An isolated security subsystem inside an SoC with its own processor, memory protection, and crypto engines.

Expert. A separate trust domain with dedicated core, encrypted and authenticated memory, TRNG, and key hierarchy. Physical design must also resist side-channel and fault attacks.

Setup time

The minimum time the data input must be stable before the capturing clock edge. Setup check: launch arrival + data delay ≤ period + capture arrival − setup.

All three levels

Beginner. How early the data must be ready before the clock tick so a memory cell grabs it correctly.

Novice. The minimum time the data input must be stable before the capturing clock edge. Setup check: launch arrival + data delay ≤ period + capture arrival − setup.

Expert. Liberty provides setup as a constraint table indexed by data and clock slew. The setup check uses late data and early capture clock under OCV, with CPPR credit and setup uncertainty applied.

side-channel attack

An attack that extracts secrets from physical effects such as power draw, timing, or electromagnetic emissions.

All three levels

Beginner. Stealing a secret by watching how a chip behaves, such as how much power it draws, instead of breaking the math.

Novice. An attack that extracts secrets from physical effects such as power draw, timing, or electromagnetic emissions.

Expert. Includes SPA/DPA, EM analysis, and timing attacks. Countermeasures include masking, hiding (constant-power logic, noise), and protocol-level key updates, and they are validated by measurement on silicon.

silicon interposer

A passive silicon die with fine wiring and through-silicon vias. Logic dies and HBM stacks sit on top of it (2.5D packaging).

All three levels

Beginner. A thin slice of silicon that acts like a miniature circuit board, wiring several chips together side by side.

Novice. A passive silicon die with fine wiring and through-silicon vias. Logic dies and HBM stacks sit on top of it (2.5D packaging).

Expert. Provides micrometer-scale routing between dies at far higher density than an organic substrate. Its own size can exceed one reticle, and its yield, cost, and warpage become part of the product’s risk.

Simulated annealing

An optimization method that proposes random moves, always accepts improvements, and accepts a worsening move with probability exp(−Δcost/T). The temperature T is lowered slowly, so the search becomes greedier over time.

All three levels

Beginner. A search method that tries random swaps and sometimes accepts a worse one early on, the way cooling metal settles into a good arrangement.

Novice. An optimization method that proposes random moves, always accepts improvements, and accepts a worsening move with probability exp(−Δcost/T). The temperature T is lowered slowly, so the search becomes greedier over time.

Expert. The basis of TimberWolf (1985). Quality can be high, but convergence is slow and it scales poorly to millions of cells, so it survives mainly in small problems where its cost is affordable.

Single-event effect (SEE)

An effect caused by the charge from a single particle strike. Includes SEU, SET, SEFI (non-destructive) and SEL (potentially destructive).

All three levels

Beginner. What happens when one fast particle hits a chip: a flipped bit, a glitch, or worse.

Novice. An effect caused by the charge from a single particle strike. Includes SEU, SET, SEFI (non-destructive) and SEL (potentially destructive).

Expert. Characterized by cross-section versus LET in heavy-ion tests and combined with an orbit’s particle spectrum to predict rates per device-day.

Single-event functional interrupt (SEFI)

An upset in control logic that causes a functional “hiccup.” A soft SEFI clears with a reset or reprogram; a hard SEFI needs a power cycle.

All three levels

Beginner. A particle hit that makes a chip freeze or misbehave until it is reset.

Novice. An upset in control logic that causes a functional “hiccup.” A soft SEFI clears with a reset or reprogram; a hard SEFI needs a power cycle.

Expert. Often caused by upsets in state machines, configuration or test logic. Can resemble SEL on a tester when current rises, so classification needs visibility into device state.

Single-event latch-up (SEL)

A destructive SEE that triggers parasitic thyristor structures in CMOS, causing high current until power is removed.

All three levels

Beginner. A particle hit turns on a hidden short circuit inside the chip, which can burn it out.

Novice. A destructive SEE that triggers parasitic thyristor structures in CMOS, causing high current until power is removed.

Expert. Specified as an LET threshold (for example above 125 MeV·cm²/mg). Addressed by process (epitaxial or SOI substrates), guard rings and well taps, and system current limiting with power cycling.

Single-event transient (SET)

A voltage glitch in combinational logic. It becomes an error if a flip-flop captures it at a clock edge.

All three levels

Beginner. A brief false pulse on a wire caused by a particle hit.

Novice. A voltage glitch in combinational logic. It becomes an error if a flip-flop captures it at a clock edge.

Expert. A transient on a data path near the clock edge can be captured by all three TMR copies at once; SET filters, triplicated logic and timing skew between copies address this.

Single-event upset (SEU)

A non-destructive change of state in a memory cell or flip-flop caused by one particle strike.

All three levels

Beginner. A particle flips a stored 1 to a 0 (or the reverse). Nothing is damaged, but the data is wrong.

Novice. A non-destructive change of state in a memory cell or flip-flop caused by one particle strike.

Expert. Mitigated by EDAC on arrays, TMR or DICE on registers, and scrubbing. Multi-bit upsets from one strike defeat simple codes and closely placed redundant cells.

Single-point fault metric (SPFM)

The fraction of safety-relevant hardware failure rate that is not single-point or residual faults. Targets: ≥90% for ASIL B, ≥97% for C, ≥99% for D.

All three levels

Beginner. The share of possible faults that the chip’s checkers would catch before they cause harm.

Novice. The fraction of safety-relevant hardware failure rate that is not single-point or residual faults. Targets: ≥90% for ASIL B, ≥97% for C, ≥99% for D.

Expert. Computed from FMEDA failure rates and diagnostic coverage, with coverage claims backed by fault-injection evidence.

Skew group

A set of clock sinks that CTS balances against each other. Sinks in different groups need not be balanced.

All three levels

Beginner. A set of memory cells that must all get the clock at about the same time.

Novice. A set of clock sinks that CTS balances against each other. Sinks in different groups need not be balanced.

Expert. Skew groups let CTS ignore pairs that never talk (unrelated domains, test-only flops), define balancing through generated clocks, and give macros or I/O flops their own latency targets.

Slack

Required time minus arrival time for a timing path. Negative slack means the path violates its constraint.

All three levels

Beginner. How much spare time a signal has before it would arrive too late. Positive is good; negative means it’s late.

Novice. Required time minus arrival time for a timing path. Negative slack means the path violates its constraint.

Expert. Per-endpoint margin against a setup or hold check. WNS is the worst slack in a path group and TNS sums the negative slacks. Synthesis reports slack with ideal clocks and estimated wires, so teams often target a positive margin to absorb later degradation.

Slack

Required time minus arrival time for a timing check. Negative slack is a violation; WNS/TNS summarize the worst and total negative slack.

All three levels

Beginner. Spare time. Positive means the deadline is met; negative means it is missed.

Novice. Required time minus arrival time for a timing check. Negative slack is a violation; WNS/TNS summarize the worst and total negative slack.

Expert. Setup and hold slack are computed under different corners and early/late assumptions, and both include uncertainty and CPPR. A path can show positive setup slack and negative hold slack at once.

SoC

System-on-chip: a single die integrating CPUs, GPU, memory controllers, accelerators, I/O, and often analog and RF blocks.

All three levels

Beginner. A system-on-chip: one chip that holds almost everything a device needs, from processors to radios.

Novice. System-on-chip: a single die integrating CPUs, GPU, memory controllers, accelerators, I/O, and often analog and RF blocks.

Expert. Mostly an integration problem: licensed and reused IP, interconnect, clock and power domains, and chip-level verification of interactions no single IP team owns.

Spare cell

Unconnected gates (inverters, NANDs, flip-flops) spread across the die during placement with inputs tied off, ready to be wired in by a metal-only ECO.

All three levels

Beginner. Extra unused parts scattered around the chip so a late bug fix can be made by changing only the wiring.

Novice. Unconnected gates (inverters, NANDs, flip-flops) spread across the die during placement with inputs tied off, ready to be wired in by a metal-only ECO.

Expert. Placed in a uniform distribution so any late logic change has spare gates nearby. They cost area and leakage. Their mix and density is a project decision; too few nearby spares means long ECO wires and timing hits.

Split manufacturing

An untrusted foundry builds the transistors and lower metal layers (FEOL); a trusted facility adds the upper metal layers (BEOL) that complete the wiring.

All three levels

Beginner. Making a chip in two factories so neither one sees the whole design.

Novice. An untrusted foundry builds the transistors and lower metal layers (FEOL); a trusted facility adds the upper metal layers (BEOL) that complete the wiring.

Expert. Security depends on how much of the netlist can be inferred from the FEOL. Proximity attacks exploit placement and routing heuristics; defenses include placement perturbation, wire lifting and layout obfuscation.

Standard cell

A pre-designed, pre-characterized logic gate or flip-flop with a fixed height so that cells snap into rows. A library offers each function in several drive strengths (X1, X2, X4).

All three levels

Beginner. A small, pre-designed building block (such as a simple logic gate or a one-bit memory) that the chip is assembled from.

Novice. A pre-designed, pre-characterized logic gate or flip-flop with a fixed height so that cells snap into rows. A library offers each function in several drive strengths (X1, X2, X4).

Expert. A layout-ready cell with LEF abstract, Liberty timing/power models and often several threshold-voltage flavors. Synthesis chooses function, drive strength and flavor per instance; dont_use lists keep cells that are hard to route or poorly characterized out of the netlist.

Sum of products (SOP)

A two-level Boolean form: an OR of AND terms, such as ab + a′c. Minimizing it means using as few and as small terms as possible.

All three levels

Beginner. Writing a logic rule as a list of ‘this AND that’ cases joined by OR.

Novice. A two-level Boolean form: an OR of AND terms, such as ab + a′c. Minimizing it means using as few and as small terms as possible.

Expert. The two-level form targeted by Quine–McCluskey and Espresso. It maps directly onto PLAs but blows up for functions like parity, which is why standard-cell synthesis works on multi-level networks and uses SOP minimization only locally.

systolic array

A 2D array of multiply-accumulate cells where operands flow between neighbors each clock cycle. It computes matrix products with few memory reads.

All three levels

Beginner. A grid of tiny calculators that pass numbers to their neighbors in rhythm, so each number is reused many times instead of being fetched again.

Novice. A 2D array of multiply-accumulate cells where operands flow between neighbors each clock cycle. It computes matrix products with few memory reads.

Expert. A regular PE mesh (weight-, output-, or input-stationary) that trades flexibility for operand reuse and short wires. Utilization drops on small or oddly shaped matrices, and fill/drain latency matters for small batches.

Tap cell (well tap)

A physical-only cell that connects the n-well and p-substrate to the supply rails. Placed in a regular pattern before standard cells so no transistor is too far from a tap.

All three levels

Beginner. A tiny helper part sprinkled at regular spacing that ties the chip’s silicon to power and ground to keep it electrically stable.

Novice. A physical-only cell that connects the n-well and p-substrate to the supply rails. Placed in a regular pattern before standard cells so no transistor is too far from a tap.

Expert. LEF CLASS CORE WELLTAP. The foundry sets a maximum distance from any active area to the nearest tap to prevent latch-up, so taps go in a checkerboard at a fixed pitch (OpenROAD tapcell -distance) and are FIXED before placement.

TARA

Threat Analysis and Risk Assessment, the risk method in ISO/SAE 21434: identify assets, threat scenarios, impacts and attack paths.

All three levels

Beginner. A structured way to list what an attacker might go after and how bad it would be.

Novice. Threat Analysis and Risk Assessment, the risk method in ISO/SAE 21434: identify assets, threat scenarios, impacts and attack paths.

Expert. Feeds chip requirements such as secure boot, key storage, debug lock-down and cryptographic acceleration, and must be maintained across the vehicle lifecycle.

Technology mapping

Covering the optimized generic logic with cells from the target library so that the function is preserved and area or delay is minimized.

All three levels

Beginner. Choosing real parts from the catalog to build each piece of the simplified circuit.

Novice. Covering the optimized generic logic with cells from the target library so that the function is preserved and area or delay is minimized.

Expert. A covering problem over a subject graph (today usually an AIG). Modern mappers enumerate cuts, match cut functions against library cells by Boolean matching, pick a delay-optimal cover by dynamic programming and then recover area off the critical path.

tick-to-trade

End-to-end latency from receiving a market-data message to transmitting an order, measured on the wire.

All three levels

Beginner. The time between a price update arriving from the exchange and the trading system sending an order in response.

Novice. End-to-end latency from receiving a market-data message to transmitting an order, measured on the wire.

Expert. Benchmarks define the measurement points precisely. STAC-T0 measures from the last bit needed for the decision to the first bit of the outbound order, and it covers network I/O only, with trivial trading logic.

Timing-driven placement

Placement that uses timing analysis to find critical nets and raises their weight so the placer keeps them short.

All three levels

Beginner. Placing the parts on the slowest signal paths extra close together so signals get through in time.

Novice. Placement that uses timing analysis to find critical nets and raises their weight so the placer keeps them short.

Expert. Usually net reweighting from periodic static timing analysis on estimated parasitics. Path-based and Lagrangian formulations exist. Over-weighting a few nets can create density hot spots and hurt total wirelength.

Total ionizing dose (TID)

Cumulative ionizing radiation absorbed by the device, measured in krad(Si) or Gy(Si). It shifts transistor thresholds and raises leakage until the part degrades or fails.

All three levels

Beginner. The radiation a chip soaks up over its whole life, which slowly wears it out.

Novice. Cumulative ionizing radiation absorbed by the device, measured in krad(Si) or Gy(Si). It shifts transistor thresholds and raises leakage until the part degrades or fails.

Expert. Specified as a minimum tolerance, for example 300 krad(Si). Hardening uses process choices, enclosed-layout transistors and guard rings to cut leakage paths; dose rate and temperature during test affect the result.

Triple modular redundancy (TMR)

Three copies of a register or block feed a majority voter, so one wrong copy is outvoted.

All three levels

Beginner. Keeping three copies and going with the majority.

Novice. Three copies of a register or block feed a majority voter, so one wrong copy is outvoted.

Expert. Flip-flop-level TMR masks single upsets but not SETs captured by all three copies; full TMR triplicates voters and logic. In FPGAs, distributed TMR (everything except global routes) outperformed flip-flop-only TMR in NASA beam tests.

Trusted Foundry

The DoD program, managed by DMEA, that gives government users access to accredited suppliers for design, masks, fabrication, packaging and test of sensitive chips.

All three levels

Beginner. A government program that lets the military get chips made by factories that have been checked and approved.

Novice. The DoD program, managed by DMEA, that gives government users access to accredited suppliers for design, masks, fabrication, packaging and test of sensitive chips.

Expert. DoD program run by DMEA’s Trusted Access Program Office. It provides guaranteed access to accredited flows (MPW, prototype and production runs) for low-volume government needs, protecting integrity and confidentiality through chain-of-custody controls.

Trusted supplier (DMEA-accredited)

A supplier accredited by DMEA for one or more services: IC design, aggregation, brokering, mask making, fabrication, post-processing, packaging/assembly or test.

All three levels

Beginner. A company the Defense Department has inspected and approved to handle a step in making sensitive chips.

Novice. A supplier accredited by DMEA for one or more services: IC design, aggregation, brokering, mask making, fabrication, post-processing, packaging/assembly or test.

Expert. Accreditation covers people and processes for a specific service. DoDI 5200.44 requires custom or tailored ICs for DoD military end use in applicable systems to be procured from accredited suppliers.

UCIe

Universal Chiplet Interconnect Express, an open standard for die-to-die links covering the physical layer, protocols, and software.

All three levels

Beginner. A shared rulebook so chiplets from different makers can talk to each other inside one package.

Novice. Universal Chiplet Interconnect Express, an open standard for die-to-die links covering the physical layer, protocols, and software.

Expert. Defines standard-package (100–130 µm bump pitch, up to 25 mm reach) and advanced-package (25–55 µm pitch, up to 2 mm) PHYs, with lane repair in the advanced profile and PCIe/CXL protocol mapping.

UPF

The Unified Power Format (IEEE 1801), a Tcl-based file that describes power domains, supplies, switches, isolation, level shifting, and retention.

All three levels

Beginner. A written plan that tells the design tools which parts of the chip can be switched off and how.

Novice. The Unified Power Format (IEEE 1801), a Tcl-based file that describes power domains, supplies, switches, isolation, level shifting, and retention.

Expert. Power intent kept separate from RTL and refined through the flow. Simulation, synthesis, place-and-route, and equivalence checking all consume it, so mismatches between UPF and implementation are a classic bug source.

Useful skew

Deliberate, non-zero skew that moves timing margin from a path with spare time to a path that needs it. It helps setup on one path and costs hold margin there and setup margin on the next stage.

All three levels

Beginner. Making the clock tick reach one memory cell a bit late on purpose, to give a slow calculation more time.

Novice. Deliberate, non-zero skew that moves timing margin from a path with spare time to a path that needs it. It helps setup on one path and costs hold margin there and setup margin on the next stage.

Expert. Formalized by Fishburn as a linear program over sink latencies. Production tools apply it incrementally as concurrent clock and data (CCD) optimization, bounded by hold and by cycle constraints where skews cancel.

Utilization (placement density)

Total standard-cell area divided by available placement area. Core utilization is the average; target density is the maximum a placer allows in any local bin. Leaving 25–40% free gives room for wires and for buffers added later.

All three levels

Beginner. How full the chip’s floor is. 70% means 70% of the space is taken by parts and 30% is left open.

Novice. Total standard-cell area divided by available placement area. Core utilization is the average; target density is the maximum a placer allows in any local bin. Leaving 25–40% free gives room for wires and for buffers added later.

Expert. Distinguish global utilization from local bin density and pin density. A design can be 60% utilized overall and still have 95% bins next to macros. Placers enforce a target density per bin (OpenROAD gpl defaults to 0.7) and routability modes inflate cells where congestion is predicted.

Wire-load model

A table in the Liberty file that estimates a net’s length, capacitance and resistance from its fanout, used when no placement exists yet.

All three levels

Beginner. A rough guess at how long the wires will be, made before anything is actually laid out.

Novice. A table in the Liberty file that estimates a net’s length, capacitance and resistance from its fanout, used when no placement exists yet.

Expert. A statistical fanout-to-RC lookup. It predicts the average net reasonably but not individual nets, so critical paths are mispredicted once interconnect dominates. Placement-aware synthesis replaces it with estimates from a quick placement.