The digital chip design flow

From a sentence
to silicon.

A modern chip holds billions of transistors, and it starts as a list of goals on a page. Follow the 13 steps that turn that list into the file a factory uses to make it.

Thirteen stages take a design from specification through RTL, synthesis and physical design to a GDSII file a foundry can manufacture. Chapters include interactive simulations, real file formats and public sources.

Front-end and back-end implementation in detail: constraints, reports, signoff, advanced-node effects and the algorithms inside the tools, with every claim tied to a public source.

Explore the flow →Try the clock sim

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Click a layer to see which stage of the flow builds it.

Three depths

Pick how deep you want to go

The switch in the header sets the depth for the whole site. Every section also has its own switch, so you can go deeper on one topic without changing the rest. Here’s the same idea at each level.

Spec → GDS

The flow, layer by layer

The front end decides what the chip does. The back end decides where every transistor and wire goes.

  1. Front end · what the chip does

    01Specification
    Decide what the chip must do, how fast it must run, how much power it may use and what it may cost. Every later step is graded against this list.
    Performance, power, area and cost targets get written down along with interfaces, standards and the target process. The spec drives architecture choices and becomes the source of verification goals.
    PPA and cost targets, interface and protocol compliance, power and thermal envelope, package and I/O constraints, process selection, DFT, safety and security requirements, and schedule. Ambiguity here costs the most later, so good specs are versioned and traceable to the verification plan.
    The targetsOutline
  2. 02Architecture
    Sketch the chip's major parts, such as processors, memory and the roads between them, and decide how they work together.
    Architects split the design into blocks (cores, accelerators, memories, interconnect, I/O), model performance, and choose clocking, power domains and the memory hierarchy. Software models test ideas before any hardware is written.
    Performance modeling, microarchitecture trade-offs, interconnect and NoC topology, memory hierarchy and bandwidth, clock and power domain strategy, IP make-or-buy, partitioning with the floorplan in mind, and early power and area estimates.
    The block diagramOutline
  3. 03RTL design
    Engineers write the chip's behavior as code that describes hardware: storage elements and the logic between them.
    Register-transfer level (RTL) code in SystemVerilog or VHDL describes registers and the logic between them on every clock edge. Lint and clock-domain-crossing checks catch problems early.
    Synthesizable coding style, reset strategy, CDC and RDC structures, parameterization, lint sign-off, UPF power intent alongside the RTL, and early PPA estimation. Generators like Chisel and high-level synthesis produce RTL for some blocks.
    The behavior, as codeOutline
  4. 04Verification
    Before anything is built, teams test the design in simulation to find mistakes. Fixing a bug after manufacturing is enormously expensive.
    Testbenches (often UVM or cocotb), assertions, coverage, formal verification and emulation check that the RTL matches the spec. It often takes as much effort as the design itself, or more.
    Coverage-driven constrained-random verification, formal property checking, emulation and FPGA prototyping for software bring-up, power-aware and gate-level simulation, and the coverage criteria that define done.
    ConfidenceOutline
  5. 05Logic synthesis
    Software translates the code into a parts list of real building blocks, logic gates from a library, wired together.
    Synthesis turns RTL into a gate-level netlist of standard cells from a technology library, optimizing against timing constraints, area and power.
    Elaboration, technology-independent optimization, technology mapping, timing-driven sizing and restructuring, clock gating, retiming, physical-aware synthesis, and equivalence checking against the RTL.
    The gate netlistFull chapter
  6. 06Design for test
    Add hidden test circuitry so every manufactured chip can be checked for defects at the factory.
    Flip-flops get chained into scan chains, memories get built-in self-test, and ATPG software generates patterns that detect manufacturing faults.
    Scan insertion and compression, ATPG for stuck-at, transition and cell-aware fault models, memory and logic BIST, IEEE 1149.1 boundary scan, test-mode constraints, and test cost against coverage.
    Test accessOutline

  7. Back end · where everything goes

    07Floorplanning
    Decide where the big pieces go on the silicon, like planning the rooms before building a house.
    Set the die and core size, place I/O pads and large macros such as memories, and plan blockages and channels so later steps can place and route cleanly.
    Die and core sizing from utilization targets, macro placement and orientation, pin assignment, channels and halos, hierarchical partitioning, voltage areas for power domains, and early congestion and timing feasibility.
    The die outlineOutline
  8. 08Power planning
    Build the chip's power wiring so every part gets a steady supply.
    Rings, straps and rails form a power delivery network across the metal layers. The goal is to keep voltage drop (IR drop) and electromigration within limits.
    PDN topology and strap pitch on upper metals, via arrays, power switches for gated domains, static and dynamic IR analysis, EM limits, decap insertion, and backside power delivery at the newest nodes.
    The power gridOutline
  9. 09Placement
    Software finds a spot for each of hundreds of thousands of building blocks so the connected ones sit close together.
    Standard cells are placed into rows to keep wires short while meeting timing and avoiding congestion. Global placement, legalization and detailed placement run in sequence.
    Analytical and electrostatic global placement, timing- and congestion-driven optimization, legalization, detailed placement, and in-placement buffering, sizing and Vt swapping.
    The cell layerFull chapter
  10. 10Clock tree synthesis
    Deliver the chip's heartbeat, the clock, to every memory cell at almost the same moment.
    CTS builds a buffered tree that carries the clock to every flip-flop while controlling skew, latency and transition. Timing is then re-checked with real clock delays.
    Skew groups, useful skew, non-default rules and shielding, multi-source and mesh topologies, clock gating, OCV and CPPR, and post-CTS hold fixing.
    The clock networkFull chapter
  11. 11Routing
    Draw the actual wires connecting every block, stacked across many layers of metal.
    Global routing plans paths through a coarse grid, then detailed routing draws exact wires and vias that obey the foundry's design rules.
    Track assignment, timing- and crosstalk-driven routing, via optimization, DRC convergence, antenna fixing, and multi-patterning-aware routing at advanced nodes.
    The metal stackOutline
  12. 12Signoff
    Run the final checks that prove the chip will be fast enough, can be manufactured and matches the design.
    Static timing analysis across corners, physical verification (DRC and LVS), power and IR-drop analysis and equivalence checks must all pass before tapeout.
    Multi-corner multi-mode STA on extracted parasitics, OCV and POCV, crosstalk, DRC, LVS, ERC and antenna, IR and EM signoff, and the ECO loops that close what's left.
    Proof it worksOutline
  13. 13GDS & tapeout
    Package the finished design into a file the factory uses to make its masks, then send it off.
    The final layout is merged with metal fill and exported as GDSII or OASIS. Handing that file to the foundry is called tapeout.
    Metal fill and density checks, final DRC on the merged database, mask data preparation and the tapeout checklist. Optical proximity correction happens on the foundry side.
    The mask dataOutline

Industries

Same flow, different priorities

A satellite, a pacemaker and an AI accelerator all go from spec to GDS, but each one bends the flow around a different constraint.

AI accelerators and data centerDies as large as lithography can print, stitched together in the package and fed by stacked memory, all to keep matrix math busy.Read →Personal and edge devicesPhones, wearables, and sensors, where battery life is the spec, every square millimeter is a cost, and most of the chip is asleep most of the time.Read →AutomotiveChips that must detect their own faults, survive under the hood and ship with near-zero defects.Read →Medical devicesImplants and medical electronics, where a chip must run safely for a decade on a tiny battery and every design change is a regulatory event.Read →SpaceChips that keep working through radiation and temperature extremes, years from the nearest repair.Read →DefenseChips that must be trusted, export-controlled and kept in service for decades.Read →Fintech and tradingNanosecond trading on FPGAs, certified secure chips in payment cards and HSMs, and single-function mining ASICs.Read →

Beyond the flow

The rest of the story

Tool landscapeCommercial and open-source tools mapped stage by stage.AI in EDAMachine learning and LLMs inside today’s design flows.After tapeoutMasks, wafers, test, packaging and first silicon.GlossaryEvery term on the site, defined at your level.