Stage 2 of 13 · Front end

Architecture

Sketch the chip's major parts, such as processors, memory and the roads between them, and decide how they work together.

Architects split the design into blocks (cores, accelerators, memories, interconnect, I/O), model performance, and choose clocking, power domains and the memory hierarchy. Software models test ideas before any hardware is written.

Performance modeling, microarchitecture trade-offs, interconnect and NoC topology, memory hierarchy and bandwidth, clock and power domain strategy, IP make-or-buy, partitioning with the floorplan in mind, and early power and area estimates.

Builds The block diagram

Chapter in progress

What this chapter will cover

Partitioning into blocks and IP
Performance modeling
Memory hierarchy and interconnect
Clock and power domain strategy
Early power and area budgets

Full chapters are ready for Logic synthesis, Placement and Clock tree synthesis.