Clock tree synthesis

CTS is where the clock stops being an SDC abstraction and becomes the largest, most active net on the die. The tool builds each clock network against per-skew-group targets for skew, latency and max transition, then optimizes with propagated clocks: useful skew or concurrent clock and data (CCD) optimization for setup, buffer insertion for hold, and sizing for slew and power. The same step decides how much of each critical launch/capture pair shares a common clock path, which later determines how much CPPR credit signoff gives back under OCV derating.

Clock power is the other half of the objective. Each clock node switches every cycle, while data nodes switch only when logic values change. Published processor breakdowns put the clock network above a quarter of chip power, and at 40–44% across several Alpha generations.²¹ Production tools: Cadence Innovus (CCOpt), Synopsys IC Compiler II and Fusion Compiler, and open-source OpenROAD TritonCTS, which builds a generalized H-tree over k-means sink clusters.⁸

Beyond the basic files, CTS consumes multi-mode multi-corner scenarios (which corner the tree is balanced in matters), skew-group and exclude/ignore-pin definitions, and macro clock-pin insertion delays. Liberty can describe a macro’s internal clock tree with min/max_clock_tree_path timing groups, which STA includes in latency and skew reports on request.⁵ TritonCTS balances macro and register trees by inserting delay buffers and adds dummy loads to even out leaf capacitance; its inserted instances carry the prefixes clkbuf_regs, delaybuf and clkload, which makes them easy to find in the netlist.⁶ The clock nets often leave CTS with routing guides or pre-routes and NDRs attached, and are routed before signal nets.

What the targets really mean

Global skew is a proxy. Correct timing depends only on local skew between sequentially adjacent sinks, which is why useful-skew formulations work on local constraints.³ Tools still minimize skew within each skew group because a tight tree is predictable and leaves room for CCD to add deliberate offsets. The CTS outcome that matters at signoff is slack after variation, which depends on three things: latency, the uncommon fraction of each critical pair’s clock paths, and transition.

Variation, derates and CPPR

STA models on-chip variation by derating early and late paths differently, and clock paths are derated too (set_timing_derate -clock -early / -late).⁵ Flat derates are too pessimistic for deep paths and too optimistic for shallow ones. AOCV indexes the derate by logic depth and distance; POCV gives each cell a sigma (from LVF data in the library) and combines them statistically along the path.¹⁴ For a setup check, the launch clock is late and the capture clock early. On the segment both share, that is physically impossible, so CPPR credits back the early/late difference on the common path.¹³ The design consequence: two flops that split at the last buffer lose almost nothing to clock derates, while two that split at the root lose the derate on the whole tree. Shallow, low-latency trees and clustering of tightly connected flops under one branch both buy real slack.

Uncertainty before and after CTS

Clock uncertainty covers jitter and, before CTS, the skew the tree will add.⁵ Jitter varies cycle to cycle at one sink, while skew is a spatial difference.⁴ A typical flow reduces setup uncertainty after CTS to jitter plus margin, and deletes the ideal-mode set_clock_latency and set_clock_transition, since they apply only to ideal clocks.⁵ Leaving the pre-CTS numbers in place double-counts skew and sends the optimizer chasing phantom violations.

Topology trade-offs in practice

An H-tree gives balance at the cost of capacitance: its total wirelength, and therefore power, exceeds a sink-driven buffered tree’s, and symmetric structures add latency.² A mesh puts branch resistances in parallel and shares the path above the mesh among all loads, so only the short stubs below it see uncorrelated variation.²¹¹ Multisource CTS drives a mesh fabric that Toyama describes as one to two orders of magnitude sparser than a full clock mesh, fed by H-tree pre-routes, with conventional subtrees hanging off tap points.¹¹ The Alpha 21264 shows the hybrid style at processor scale: a trunk and X/H-trees fed 16 drivers of a gridded global clock, every grid wire shielded by power or ground, local gated clocks below, and 65 ps of skew measured on silicon.²

Clock gating inside the tree

An ICG’s clock pin sits upstream of the flops it gates, so its clock arrives earlier than theirs. The enable is launched by ordinary flops at full latency and captured at that earlier ICG clock, which shortens the effective window for the gating check. Pushing ICGs toward the root gates more of the tree and saves more power, but tightens enable timing; cloning an ICG to sit near its fanout does the opposite. TritonCTS’s -balance_levels keeps a similar number of levels across non-register cells such as clock gates and inverters.⁶

Generated clocks, macros and skew groups

A divided clock inherits the master’s latency up to the divider flop plus the divider’s clock-to-Q and its own tree, so a div2 domain talking to its master needs the two trees balanced at the crossing flops. Skew groups express exactly which sink sets must align: include the divider’s fanout and the master flops it exchanges data with, exclude scan-only or asynchronous sinks. Macros bring their own internal latency; TritonCTS inserts delay buffers to balance macro and register trees, with a derate knob to insert only part of the needed delay.⁶

Hold repair and the useful-skew budget

Post-CTS hold repair is where a bad tree shows. OpenROAD caps hold buffers at 20% of the instance count by default and refuses buffers that create setup violations unless told otherwise.⁷ Every picosecond of useful skew given to a setup path is a picosecond taken from hold on that pair and from setup on the downstream stage, so CCD engines search for latency adjustments that improve worst and total negative slack together.¹⁵

Power and EM

Clock nets are long, heavily loaded and switch every cycle.¹ Switching activity also drives RMS (Joule-heating) electromigration: time to failure falls as switching rate rises.¹⁶ Clock nets have the highest activity on the die, so clock drivers and trunk wires need EM checks with their true switching rate. The usual fixes are wider NDR wires, extra vias on trunk connections, and splitting large loads across several drivers.

Use the sim to reason about margins the slider set doesn’t show directly. Fold uncertainty and derates into the sliders and watch how fast the useful-skew window closes.

1. Add uncertainty. Take period 1000 ps, launch 300, capture 360, data 950: setup slack +30 ps. Model 50 ps of setup uncertainty by raising setup from 80 to 130 ps: slack −20 ps. The skew that fixed the ideal-mode path is not enough with post-CTS margins.
2. Add OCV. Derate the data path late by 5% (950 → 998 ps) and the uncommon part of the capture clock early by 5% (if 200 of its 360 ps is uncommon, capture becomes 350 ps). Setup slack falls by about 58 ps, before even counting the launch clock’s own late derate. The CPPR credit applies only to the shared segment.
3. Borrowing from the next stage. Suppose the downstream path from the capture flop has data 900 ps and launches at 300 ps into a flop clocked at 300 ps: setup slack +20 ps. After you moved this flop’s clock to 360 ps, that stage launches at 360 ps and its slack is −40 ps. Around any loop of stages the skews cancel, which is the core of Fishburn’s formulation (see Under the hood).

Two artifacts tell you whether the tree is good: the CTS summary with a skew report, and the worst setup and hold paths with the clock network expanded. Both are illustrative, in OpenROAD/OpenSTA format, times in ns.

[INFO CTS-0098] Clock net "core_clk"
[INFO CTS-0099]  Sinks 18432
[INFO CTS-0100]  Leaf buffers 912
[INFO CTS-0101]  Average sink wire length 41.27 um
[INFO CTS-0102]  Path depth 6 - 8
[INFO CTS-0207]  Dummy loads inserted 37
Total number of Clock Roots: 1.
Total number of Buffers Inserted: 1206.
Total number of Clock Subnets: 1206.
Total number of Sinks: 18432.

> report_clock_skew -setup -digits 3
Clock core_clk
  0.461 source latency u_lsu/addr_reg[3]/CK ^
 -0.389 target latency u_lsu/tag_reg[3]/CK ^
  0.050 clock uncertainty
 -0.018 CRPR
--------------
  0.104 setup skew

Startpoint: u_alu/acc_reg[12] (rising edge-triggered flip-flop clocked by core_clk)
Endpoint: u_alu/res_reg[31] (rising edge-triggered flip-flop clocked by core_clk)
Path Group: core_clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
  0.000   0.000   clock core_clk (rise edge)
  0.458   0.458   clock network delay (propagated)
  0.000   0.458 ^ u_alu/acc_reg[12]/CK (DFF_X1)
  0.121   0.579 ^ u_alu/acc_reg[12]/Q (DFF_X1)
  0.143   0.722 v u_alu/U812/ZN (NAND2_X2)
  0.208   0.930 ^ u_alu/U1033/ZN (AOI22_X1)
  0.236   1.166 v u_alu/U1207/ZN (OAI21_X2)
  0.198   1.364 ^ u_alu/U1301/ZN (XNOR2_X1)
  0.028   1.392 ^ u_alu/res_reg[31]/D (DFF_X1)
          1.392   data arrival time

  1.000   1.000   clock core_clk (rise edge)
  0.443   1.443   clock network delay (propagated)
  0.011   1.454   clock reconvergence pessimism
  0.000   1.454 ^ u_alu/res_reg[31]/CK (DFF_X1)
 -0.050   1.404   clock uncertainty
 -0.042   1.362   library setup time
          1.362   data required time
---------------------------------------------------------
          1.362   data required time
         -1.392   data arrival time
---------------------------------------------------------
         -0.030   slack (VIOLATED)

• Balanced in the wrong corner. A tree balanced at one corner skews at another, because buffer delay and wire delay scale differently with voltage and temperature. Teams choose the balancing corner deliberately and verify skew across all signoff scenarios.
• Long uncommon paths. Critical pairs that split near the root pay the full clock derate with little CPPR credit. Caught by sorting critical paths by uncommon clock latency; fixed by clustering or skew-group constraints.
• ICG enable timing. Gates placed near the root save power but leave their enable paths failing against an early clock. Look for clock-gating check violations, then clone or push ICGs toward their loads.
• Duty-cycle drift. Long chains of mismatched buffers move the duty cycle at every stage, and the minimum-pulse-width check catches it late.⁹ Use clock cells with matched edges, or inverter pairs.
• Scan mode surprises. Scan chains reconnect flops along paths with little logic, so skew that is harmless in functional mode can cause races in test mode.² Time shift mode as its own scenario.
• EM on clock drivers. High activity makes clock trunks the first to hit RMS current limits.¹⁶ Run EM checks on clock nets with their true switching activity, not a data-net default.

The problem

Given sink locations and loads, find a routing tree from the source that meets a skew target at minimum cost. Three formulations: zero-skew trees (ZST), bounded-skew trees (BST) when signoff only needs skew under a bound, and useful skew, which constrains only local skews between related sinks.³ Most algorithms split the work into topology generation (which sinks merge with which) and geometric embedding (where the internal nodes go).

H-trees and the method of means and medians

An H-tree is exactly zero-skew by symmetry but only for regular sink arrays, so it serves top-level distribution.³ The method of means and medians (Jackson, Srinivasan and Kuh, 1990) handles arbitrary sink positions top-down: split the sinks at the median into two equal halves, connect the center of mass of the whole set to the centers of mass of each half, and recurse with the split direction alternating.¹⁸³ It balances sink counts and is fast, with no skew guarantee. Bottom-up recursive geometric matching (Kahng, Cong and Robins) pairs nearby subtrees and achieves near-zero pathlength skew in practice, still without a guarantee.¹⁸

Tsay’s exact zero skew

Tsay (1991) was the first to guarantee exact zero skew, under the Elmore model. It merges two zero-skew subtrees bottom-up at a tapping point on the wire joining their roots.¹⁸ With subtree delays t₁, t₂, downstream capacitances C₁, C₂, a connecting wire of length L, and per-unit resistance r and capacitance c, equalizing the Elmore delay from the tapping point to both sides gives the fraction z of the wire on subtree 1’s side:

z = [t₂ − t₁ + rL(C₂ + cL/2)] / [rL(C₁ + C₂ + cL)]

If 0 ≤ z ≤ 1 the tap lies on the wire. Otherwise one subtree is too slow, and the algorithm elongates (snakes) the wire on the faster side until delays match.¹⁹ Buffered trees apply the same merge per stage, since a buffer hides its subtree’s capacitance from upstream.¹⁹

Deferred-merge embedding (DME)

Earlier methods fixed each internal node’s location as soon as it was computed. DME, found independently by three groups in 1992, defers that choice. Given a topology, a bottom-up pass computes for each internal node a merging segment: the locus of all points where the two child subtrees can join with minimum added wire and zero skew. Under Manhattan distance these loci are Manhattan arcs (segments at 45°), and merging two arcs yields another arc. A top-down pass then picks the root anywhere on its segment and places each child at the point of its segment nearest the parent.¹⁸¹⁹ Kahng and Tsao summarize DME as a linear-time algorithm that optimally embeds any given topology with exact zero skew and minimum total wirelength. Its limitation is that it needs the topology as input, so it is paired with topology generators such as matching or greedy merging.¹⁸³

Bounded-skew trees (BST/DME)

Zero skew wastes wire when signoff tolerates some skew. BST/DME replaces merging segments with merging regions, the loci of feasible embedding points that keep skew within a bound B, then embeds top-down as before. It works under both pathlength and Elmore delay, and sweeping B gives a smooth trade-off between skew and wirelength; at B = 0 it reduces to DME and at unbounded skew it approaches a Steiner tree.²⁰

Elmore delay and its limits

For an RC tree, the Elmore delay to a node sums, over each resistor on the path from the source, that resistance times all capacitance downstream of it. It is the first moment of the impulse response, which makes it additive along a path and cheap enough to evaluate inside merge loops.¹⁷ Gupta, Tutuianu and Pileggi showed that it acts as a delay bound for RC trees, even with general input signals.¹⁷ It is often inaccurate but faithful: reducing Elmore delay almost always reduces true delay, so it ranks choices well.¹⁷ It knows nothing about input slew, nonlinear driver behavior or inductance, and skew is a small difference of two large delays, so computing it needs far more accuracy than computing either delay alone.² Modern CTS therefore builds with characterized lookup tables. TritonCTS characterizes buffered wire segments on the fly from Liberty data and selects segments from that table.⁶

Buffer insertion: van Ginneken’s dynamic program

Van Ginneken (1990) finds optimal buffer positions on a fixed tree under Elmore wire delay and a linear buffer model. Working from sinks to source, each candidate solution at a node is a pair (Q, C): required arrival time and downstream capacitance. At each legal buffer position the algorithm also considers a buffered option, merges candidate lists at branch points, and discards dominated candidates, those with more load and less required time than another. Run time is O(n²) in candidate positions. Lillis, Cheng and Lin extended it to b buffer types in O(b²n²), and Li and Shi reduced that to O(bn²) by showing the useful candidates lie on a convex hull in the (Q, C) plane.²¹ For clocks the objective changes from maximum slack to balance and power, but the candidate-and-prune structure carries over. TritonCTS uses dynamic programming over its generalized H-tree to choose the minimum-power topology and buffering that meets latency and skew targets, with capacitated k-means for sink clustering.⁸

Clock mesh analysis

A mesh breaks the assumptions STA delay calculation relies on: many drivers short together, paths reconverge, and the skew between mesh-buffer inputs feeds into the output. SPICE handles this accurately but slowly, and simplified models miss slew and input-skew effects, which is why research on fast mesh timing (including learned models trained on SPICE) continues.¹² Design flows typically simulate the mesh and its drivers in SPICE at a few corners, then annotate the resulting stub-input arrivals and slews back into STA for the local trees below.

Useful-skew scheduling as an LP

Fishburn (1990) posed skew scheduling as a linear program. Assign each register i a latency x_i. For every path i → j with delays d_min and d_max:

• setup: x_i + d_max + t_setup ≤ x_j + T
• hold: x_i + d_min ≥ x_j + t_hold

Minimize T, or for a fixed T maximize the smallest margin across all constraints. Fishburn named the two hazards zero-clocking (setup) and double-clocking (hold), and on a 4-bit ripple-carry adder with accumulator cut the minimum period from 9.5 ns with zero skew to 7.5 ns with scheduled skew.² Every constraint bounds a difference x_j − x_i, so for fixed T the system is a set of difference constraints on a constraint graph: feasible exactly when the graph has no negative cycle, which Bellman–Ford checks. Summing setup constraints around any cycle of k registers cancels every x, leaving T ≥ (Σ(d_max + t_setup)) / k. Skew can redistribute time along a loop but cannot shrink the loop’s average. Tools solve incremental, physically constrained versions of this problem after CTS, because each latency change must be realized with real buffers on a real tree.¹⁵