Chapter in progress
What this chapter will cover
- Die size and utilization
- Macro placement
- I/O and pin planning
- Hierarchical partitioning
- Voltage areas
Full chapters are ready for Logic synthesis, Placement and Clock tree synthesis.
Stage 7 of 13 · Back end
Floorplanning
Decide where the big pieces go on the silicon, like planning the rooms before building a house.
Set the die and core size, place I/O pads and large macros such as memories, and plan blockages and channels so later steps can place and route cleanly.
Die and core sizing from utilization targets, macro placement and orientation, pin assignment, channels and halos, hierarchical partitioning, voltage areas for power domains, and early congestion and timing feasibility.
Builds The die outline