Chapter in progress
What this chapter will cover
- Static timing analysis and corners
- Parasitic extraction
- DRC and LVS
- IR drop and EM signoff
- ECOs
Full chapters are ready for Logic synthesis, Placement and Clock tree synthesis.
Stage 12 of 13 · Back end
Signoff
Run the final checks that prove the chip will be fast enough, can be manufactured and matches the design.
Static timing analysis across corners, physical verification (DRC and LVS), power and IR-drop analysis and equivalence checks must all pass before tapeout.
Multi-corner multi-mode STA on extracted parasitics, OCV and POCV, crosstalk, DRC, LVS, ERC and antenna, IR and EM signoff, and the ECO loops that close what's left.
Builds Proof it works