Stage 6 of 13 · Front end
Add hidden test circuitry so every manufactured chip can be checked for defects at the factory.
Flip-flops get chained into scan chains, memories get built-in self-test, and ATPG software generates patterns that detect manufacturing faults.
Scan insertion and compression, ATPG for stuck-at, transition and cell-aware fault models, memory and logic BIST, IEEE 1149.1 boundary scan, test-mode constraints, and test cost against coverage.
Builds Test access
Chapter in progress
Full chapters are ready for Logic synthesis, Placement and Clock tree synthesis.