Stage 1 of 13 · Front end
Decide what the chip must do, how fast it must run, how much power it may use and what it may cost. Every later step is graded against this list.
Performance, power, area and cost targets get written down along with interfaces, standards and the target process. The spec drives architecture choices and becomes the source of verification goals.
PPA and cost targets, interface and protocol compliance, power and thermal envelope, package and I/O constraints, process selection, DFT, safety and security requirements, and schedule. Ambiguity here costs the most later, so good specs are versioned and traceable to the verification plan.
Builds The targets
Chapter in progress
Full chapters are ready for Logic synthesis, Placement and Clock tree synthesis.