Beyond the flow

AI in EDA

Where machine learning and language models show up in chip design today, and where the evidence is thin.

Chapter in progress

What this page will cover

Optimization

  • ML-driven design-space exploration for PPA
  • Reinforcement learning for macro placement, and the debate around it
  • Predicting congestion and timing before routing

Language models

  • Generating and reviewing RTL
  • Writing testbenches and assertions
  • Agentic flows that drive tools from a spec

Limits

  • Correctness and verification burden
  • Training data and IP
  • How to read published results critically

Meanwhile, the Synthesis, Placement and Clock tree synthesis chapters are complete.