Stage 4 of 13 · Front end

Verification

Before anything is built, teams test the design in simulation to find mistakes. Fixing a bug after manufacturing is enormously expensive.

Testbenches (often UVM or cocotb), assertions, coverage, formal verification and emulation check that the RTL matches the spec. It often takes as much effort as the design itself, or more.

Coverage-driven constrained-random verification, formal property checking, emulation and FPGA prototyping for software bring-up, power-aware and gate-level simulation, and the coverage criteria that define done.

Builds Confidence

Chapter in progress

What this chapter will cover

Testbenches, UVM and cocotb
Assertions and functional coverage
Formal verification
Emulation and FPGA prototyping
Gate-level and power-aware simulation

Full chapters are ready for Logic synthesis, Placement and Clock tree synthesis.