Chapter in progress
What this chapter will cover
- Rings, straps and rails
- IR drop, static and dynamic
- Electromigration
- Power gating and switches
- Backside power delivery
Full chapters are ready for Logic synthesis, Placement and Clock tree synthesis.
Stage 8 of 13 · Back end
Power planning
Build the chip's power wiring so every part gets a steady supply.
Rings, straps and rails form a power delivery network across the metal layers. The goal is to keep voltage drop (IR drop) and electromigration within limits.
PDN topology and strap pitch on upper metals, via arrays, power switches for gated domains, static and dynamic IR analysis, EM limits, decap insertion, and backside power delivery at the newest nodes.
Builds The power grid