Stage 3 of 13 · Front end

RTL design

Engineers write the chip's behavior as code that describes hardware: storage elements and the logic between them.

Register-transfer level (RTL) code in SystemVerilog or VHDL describes registers and the logic between them on every clock edge. Lint and clock-domain-crossing checks catch problems early.

Synthesizable coding style, reset strategy, CDC and RDC structures, parameterization, lint sign-off, UPF power intent alongside the RTL, and early PPA estimation. Generators like Chisel and high-level synthesis produce RTL for some blocks.

Builds The behavior, as code

Chapter in progress

What this chapter will cover

Registers, combinational logic and the clock
SystemVerilog for synthesis
Clock domain crossings
Lint and CDC sign-off
Power intent (UPF)

Full chapters are ready for Logic synthesis, Placement and Clock tree synthesis.