At a glance
Where the flow bends
- 01Specification
The headline requirement is how long the battery lasts, so the spec says how much energy each everyday task may use.
Specs give energy or current budgets per use case (standby, music playback, always-on sensing) alongside die-area and unit-cost targets.
Power is specified per mode and per use case, including leakage budgets at hot corners and wake-up latency limits. Security certification goals and the list of RF and analog IP are fixed here too.
- 02Architecture
The chip is divided into zones that can be switched off separately, with one small zone always awake to listen for events.
Architects define power domains, an always-on island, voltage and frequency operating points, and which jobs go to dedicated engines such as an NPU or DSP instead of the CPU.
The power-state table is an architectural artifact: legal domain combinations, transition sequences, and retention strategy. Most IP is licensed or reused, so architecture is largely integration and power-state design.
- 04Verification
Engineers test every combination of zones being on and off, because a zone waking up wrongly can freeze the device or drain the battery.
Power-aware simulation reads the UPF power intent and models domains switching off, so tests check isolation, retention, and power-up sequences as well as logic.
Coverage must include power-state transitions, corrupted outputs from off domains, retention save/restore, and reset ordering. Static checks verify isolation and level-shifter placement against UPF before and after synthesis.
- 05Logic synthesis
The tools pick slower, less leaky building blocks wherever there is time to spare, and add the special parts the power plan needs.
Synthesis uses multiple threshold-voltage libraries, inserts clock gating, and adds isolation cells, level shifters, and retention flops from the UPF.
Leakage recovery swaps non-critical cells to high-Vt after timing closes. UPF-driven insertion must be equivalence-checked, and area optimization matters because area is unit cost at high volume.
- 07Floorplanning
Each switchable zone gets its own region, and sensitive radio circuits are kept away from noisy digital logic.
The floorplan defines voltage areas for each power domain, reserves rows for power switches, and separates analog and RF blocks from digital switching noise.
Voltage areas, always-on routing channels, switch placement, and guard rings or substrate taps around analog and RF macros are fixed here. Die area is minimized aggressively.
- 08Power planning
Power wiring includes switches that cut supply to sleeping zones, and they must turn back on gently.
Switched supply rails sit behind header or footer power switches, with separate always-on rails for logic that must stay awake.
Switch count and daisy-chaining set wake-up time and in-rush current. Always-on rails must reach retention cells and isolation cells inside switched domains.
- 12Signoff
Final checks run at many voltages and temperatures, including very low voltages where chips become slower and less predictable.
Timing and power signoff covers every operating point and power mode, with leakage checked at high temperature where it is worst.
Multi-mode multi-corner analysis multiplies with DVFS points and domain voltage combinations. Low-voltage corners need variation-aware timing, and leakage is signed off at the hot corner.
Phones, watches, earbuds, and tiny sensors all run on batteries. For these products, battery life is the most important number, and chip designers work backward from it.
The trick is that the chip is asleep most of the time. Think of a house at night: you turn off the lights in empty rooms, but the fridge and the doorbell stay on. A phone chip does the same with , cutting power to parts it is not using while a small section listens for a tap or a message.
These chips also sell in huge numbers, so each one must be cheap. A smaller chip costs less to make, and that saving is multiplied by millions of devices.
Power has two parts. Dynamic power, roughly A × C × V² × f, comes from switching. Leakage flows whenever a transistor is powered, even when idle, and can represent 20–40% of a microprocessor’s power budget in recent processes.1 Edge chips attack both:
- Clock gating stops the clock to idle logic.
- Power gating uses header or footer switches to cut the supply to idle blocks.
- lowers voltage and frequency when the workload allows.
- libraries trade speed for leakage cell by cell.1
Designers write down which blocks can turn off, and how, in a file. UPF is the IEEE 1801 standard for power intent, and it drives both verification and implementation.2
An edge is best understood as a state machine of power modes. Each mode has its own set of live domains, voltages, and clocks, and every transition needs isolation, level shifting, retention or state reload, and sequencing. The power savings are large, but each new domain adds verification work.
The Michigan Micro Mote team describes exactly this cost. Their chips use several power domains to minimize leakage, isolation and level conversion were largely manual because tool support lagged their aggressive power gating, and as a result they often did not simulate every power state before fabrication.3
- Battery life. People judge a phone or watch by how long it lasts, so energy use is the first requirement.
- Cost. Making the chip smaller makes each one cheaper, and that adds up over millions of units.
- Everything on one chip. Processors, radios, camera processing, and AI engines share one piece of silicon to save space and power.
- Security. Your fingerprints and payment keys live on the chip, in a locked-off area called a .
Area is cost. In a standard textbook example on a 300 mm wafer, doubling die area from 60 mm² to 120 mm² raises cost per good die 2.52×, because fewer dies fit and fewer of them work.5 At phone volumes, a few square millimeters is real money.
Integration. RF CMOS puts radio, analog, and digital circuits on one chip, and it is used in the transceivers of modern phones, Bluetooth, and Wi-Fi.6 Most blocks in an SoC are licensed or reused IP, so integration and power-state design are much of the job.
On-device AI. Phone SoCs now include an . A 2019 survey of chipsets from Qualcomm, HiSilicon, Samsung, MediaTek, and Unisoc found mobile AI accelerator performance nearly doubling with each SoC generation.7
Security. Apple describes its Secure Enclave as a dedicated secure subsystem integrated into the SoC, isolated from the main processor, with its own processor, memory protection engine, true random number generator, AES engine, and public key accelerator.8
Mixed-signal coexistence. Digital switching injects noise into the shared substrate, which reaches sensitive analog and RF circuits. Standard mitigations include physical separation, careful placement of substrate contacts, guard rings and wells, and controlled transition times and power routing.9 These choices land in the floorplan and power plan, not in RTL.
Side channels. Power consumption depends on the data being processed, so power traces can reveal secret keys. Differential power analysis is practical, non-invasive, and works even when the crypto is a small fraction of total chip power.10 Apple notes that dedicating the Secure Enclave Processor to the enclave helps prevent that depend on malicious software sharing the same core.8 Physical leakage still needs countermeasures in the crypto hardware itself.
Leakage floor. Standby battery life is set by the always-on domain and any retention supplies. Their leakage at high temperature often decides library choice for that region.
- Write a power plan. Alongside the design, engineers write a separate file that says which parts can switch off and how.
- Test every on/off combination. A part that wakes up wrong can freeze the device or quietly drain the battery.
- Keep noisy and sensitive parts apart. Radio circuits are placed away from busy digital logic.
- Check at low voltage and high heat. Chips are slower when the voltage is low and leak more when they are hot, so both cases are checked.
The power intent lives in UPF, separate from the RTL. Simulation, synthesis, and place-and-route all read the same file.2 A trimmed, illustrative example for a switchable NPU domain:
# Power intent for a switchable NPU domain (IEEE 1801 style, trimmed)
create_power_domain PD_AON -include_scope
create_power_domain PD_NPU -elements {u_npu}
create_supply_net VDD_AON
create_supply_net VDD_NPU_SW
create_power_switch SW_NPU -domain PD_NPU \
-input_supply_port {vin VDD_AON} \
-output_supply_port {vout VDD_NPU_SW} \
-control_port {sleep npu_sleep} \
-on_state {on vin {!sleep}}
set_isolation ISO_NPU -domain PD_NPU -applies_to outputs \
-clamp_value 0 -isolation_signal npu_iso -isolation_sense high
set_retention RET_NPU -domain PD_NPU \
-save_signal {npu_save high} -restore_signal {npu_restore low}- 1L3The NPU instance gets its own domain so it can be powered off independently.
- 2L8A power switch feeds the NPU’s virtual rail from the always-on supply.
- 3L14Isolation clamps NPU outputs to 0 while it is off, so floating values never reach live logic.
- 4L17Retention flops save state before power-down and restore it after wake-up.
From this file, synthesis inserts , level shifters, and , and power-aware simulation corrupts the outputs of any domain that is off so tests catch missing isolation. Synthesis also inserts clock gating and assigns multi-Vt cells.
Verification. Coverage targets include every legal power state, every transition, retention save/restore, and reset ordering. Cold boot is a special case: the Micro Mote team needed a dedicated power-on reset for its isolation network because even the nominally always-on signals are still rising.3 Run static UPF checks on RTL, on the netlist, and after place-and-route.
Implementation. Each switched domain gets a voltage area, switch cells, and always-on routing for retention supplies and isolation enables. The M3 chips gave each power domain its own clock network so the clock tree would never unexpectedly cross a domain boundary.3 Analog and RF macros get guard rings and substrate taps.9
Signoff. Corners multiply: DVFS points × domain voltage combinations × process × temperature. Near-threshold operating points widen delay spread, so they need variation-aware timing margins.4 Leakage is signed off hot, and dynamic power is checked against use-case activity profiles.
Researchers at the University of Michigan built a complete computer that fits in about a cubic millimeter.3 It stacks several tiny layers holding a processor, memory, sensors, a radio, a battery, and solar cells.11
An early version was small enough to sit inside a human eye and monitor pressure for glaucoma. In standby it used only 35 picowatts, a tiny fraction of what a phone uses when asleep.11 The Computer History Museum put the Micro Mote on display as the world’s smallest computer.
The Micro Mote (M3) is an extreme edge device, which makes its trade-offs easy to see.3
- Stacked dies. Chips from 65, 130, and 180 nm processes are thinned from 300 to 150 µm, stacked in a stair-step, and wire-bonded between layers.
- Energy budget. Active power is tens of µW while the solar harvester charges at only tens of nW, so the system spends almost all of its time asleep.
- Tiny batteries. The thin-film batteries are about 1 mm² and hold 0.5–5 µAh. At shallow discharge they last 10,000+ cycles. At 60% discharge or more, capacity can fall off in tens of cycles.
- Reuse. The team built more than a dozen systems by designing modular, reusable layers with a shared bus and coordinated power states.
The project’s lessons map directly onto the flow.3
- Power intent outran tools. Isolation and level conversion between many power domains were largely manual, so not every power state was simulated before tapeout.
- Three spins per new block. First a large debug chip full of test points, then a form-factor chip with most debug removed, then a third spin to fix minor issues and scale production.
- Corners from the field. Chips tested only at 25 °C behaved differently implanted at 40 °C, which showed the need to design for wider temperature range and its effect on power draw. Some 180 nm chips were light-sensitive and needed black epoxy, with a clear window over the solar cell.
- Programming and debug. The stacks are too small for wires, so the team added an ultra-low-power optical receiver for programming. Once sealed, the radio is the only output.
Sources
- Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and StandardsDynamic and leakage power, clock gating, power gating with header/footer switches, multi-Vt, DVFS.
- IEEE 1801-2024: IEEE Standard for Design and Verification of Low-Power Energy-Aware Electronic SystemsUPF: specifying power intent for verification and implementation; free through IEEE GET.
- Lessons from Five Years of Making Michigan Micro MotesPower domains, manual isolation and level conversion, 3-spin model, stacking, power budget, temperature lessons.
- Near-Threshold Computing: Reclaiming Moore’s Law Through Energy Efficient Integrated CircuitsNear-threshold energy and delay trade-offs; subthreshold minimum-energy point.
- IC Manufacturing, Cost, Power, and Dependability (COE 501 lecture slides)Die yield and die cost formulas with a worked example of cost versus die area.
- RF CMOSRF, analog, and digital circuits integrated on one CMOS chip; used in phone and wireless transceivers.
- AI Benchmark: All About Deep Learning on Smartphones in 2019Mobile AI accelerators from five SoC vendors; performance nearly doubling each generation.
- The Secure Enclave (Apple Platform Security)Dedicated secure subsystem in the SoC with its own processor, memory protection, TRNG, AES engine, PKA.
- Substrate Coupling in Digital Circuits in Mixed-Signal Smart-Power SystemsSubstrate noise in mixed-signal ICs and mitigation by separation, substrate contacts, guard rings.
- Introduction to differential power analysisPower measurements leak secret keys; attacks are practical and non-invasive; countermeasures.
- The World’s Smallest ComputerMicro Mote components and the 35 pW standby power of the glaucoma-monitor version.